EP80579 Datasheet, PDF (1018/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 26-48. Offset 64h: PORTSC - Port N Status and Control Register (Sheet 3 of 5)
Description: Port 1 64 - 67h, Port 2 68 - 6Bh
View: PCI
BAR: MBAR
Bus:Device:Function: 0:29:7
Offset Start: 64h
Offset End: 67h
View: PCI
BAR: MBAR
Bus:Device:Function: 0:29:7
Offset Start: 68h
Offset End: 6Bh
Size: 32 bit
Default: 00003000h
Power Well: Suspend
Bit Range
Bit
Acronym
Bit Description
Sticky
Line Status: These bits reflect the current logical levels of
the D+ (bit 11) and D- (bit 10) signal lines. These bits are
used for detection of low-speed USB devices prior to the port
reset and enable sequence. This field is valid only when the
port enable bit is zero and the current connect status bit is
set to a one.
The encoding of the bits is as follows:
Bit Reset
Value
Bit Access
11 :10
Bits[11:10] USB State Interpretation
LS
00b
SE0
Not Low-speed device, perform
EHCI reset
10b
J-state
Not Low-speed device, perform
EHCI reset
01b
K-state
Low-speed device, release
ownership of port
11b
Undefined
Not Low-speed device, perform
EHCI reset
0h
RO
09
Reserved Reserved.
Port Reset:
0 = Port is not in Reset (default).
1 = Port is in Reset.
When software writes a one to this bit (from a zero), the bus
reset sequence as defined in the USB Rev. 2.0 Specification is
started. Software writes a zero to this bit to terminate the
bus reset sequence. Software must keep this bit at a one long
enough to guarantee the reset sequence, as specified in the
USB Rev. 2.0 Specification, completes.
Note: When software writes this bit to a one, it must also
write a zero to the Port Enable bit.
Note: When software writes a zero to this bit, there may be
a delay before the bit status changes to a zero. The
bit status will not read as a zero until after the reset
has completed. If the port is in high-speed mode
08
PR
after reset is complete, the host controller will
automatically enable this port (e.g., set the Port
Enable bit to a one). A host controller must
terminate the reset and stabilize the state of the port
within 2 ms of software transitioning this bit from a
one to a zero. For example, if the port detects that
the attached device is high-speed during reset, then
the host controller must have the port in the enabled
state within 2 ms of software writing this bit to a
zero.
The HCHalted bit in the USB2STS register must be a zero
before software attempts to use this bit. The host controller
may hold Port Reset asserted to a one when the HCHALTED
bit is a one.
The Run/Stop bit in the Command Register must be set in
order for the Port Reset bit to be cleared.
0h
0h
RW
Intel^® EP80579 Integrated Processor Product Line Datasheet
1018
August 2009
Order Number: 320066-003US