EP80579 Datasheet, PDF (1503/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
37.6.5.12 TSPMT – TCP Segmentation Pad and Minimum Threshold Register
This register specifies fields affecting hardware behavior during TCP Segmentation
operations. For normal (non TCP Segmentation) operations, the transmit DMA never
begins servicing an individual data descriptor unless the transmit Packet Buffer has
sufficient room to accept all of the data associated with the descriptor. However, for TCP
Segmentation operations, it may be desirable to use a data descriptor which refers to a
larger contiguous buffer in host memory than is actually allocated for the transmit
Packet Buffer. For this case, the transmit DMA must be able to initiate smaller transfers
than the entire descriptor's data length field (i.e., during TCP segmentation, the
transmit DMA does not wait until the entire descriptor's data can fit in the packet
buffer).
When performing TCP segmentation, the packet prototype header initially transferred
by DMA is stored internally and updated as each packet of the TCP segmentation
operation is composed. As data for subsequent TCP segments is DMA'd into the
controller, the frame header for each segment is dynamically inserted in front of the
frame payload data stream prior to being written to the packet buffer. In order to
obtain the most efficient use of burst DMA operations, the transmit DMA will attempt to
fetch as much data from a descriptor as possible, rather than limiting itself to bursting
each data segment individually. However, to do this, sufficient packet-buffer space
must be reserved to account for all headers which will be inserted into the fetched data
stream, as the burst may span multiple data segments. The calculation of how much
packet buffer space should be reserved is dependent on the MSS being used in the
packet header, the maximum-sized data buffer pointed to by a descriptor, and the
current header size. Such calculation cannot be easily calculated in hardware, and is
left to software to pre-calculate for the worst-case usage.
The transmit DMA will further refrain from initiating service of a new data descriptor
unless sufficient packet buffer space exists to at least fetch a full data segment or
complete a partially-fetched segment. This additionally helps to reduce the number of
small DMA bursts and reducing the efficiency of the host interface.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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