EP80579 Datasheet, PDF (907/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 24-19. Offset 00h: HSTS: Host Status Register (Sheet 2 of 2)
Description:
View: PCI
BAR: SM_BASE (IO)
Bus:Device:Function: 0:31:3
Offset Start: 00h
Offset End: 00h
Size: 8 bit
Default: 00h
Power Well: Resume
Bit Range
04
03
02
01
00
Bit Acronym
Bit Description
Sticky
FAIL
MCERR
DERR
INTR
HBSY
Failed:
0 = Software clears this bit by writing a 1 to it.
1 = The source of the interrupt or SMI# was a failed
bus transaction. This bit is set in response to the
KILL bit being set to terminate the host
transaction.
Machine Check Error:
0 = Software clears this bit by writing a 1 to it.
1 = The source of the interrupt of SMI# was a
transaction collision.
Device Error:
0 = Software clears this bit by writing a 1 to it, then
deasserts the interrupt or SMI#.
1 = The source of the interrupt or SMI# was due to one
of the following:
• Illegal Command Field·
• Unclaimed Cycle (host initiated)
• Host Device Time-out Error
• CRC Error
Interrupt: When set, this indicates that the source of
the interrupt or SMI# was the successful completion of
its last command.
Host Busy:
0 = Cleared when the current transaction is completed
1 = Indicates that the CMI is running a command from
the host interface. No SMB registers must be
accessed while this bit is set, except the BLOCK
DATA BYTE Register. The BLOCK DATA BYTE
Register can be accessed when this bit is set only
when the SMB_CMD bits in the Host Control
Register are programmed for Block command or
I²C Read command. This is necessary in order to
check the DONE_STS bit.
Bit Reset
Value
0h
0h
0h
0h
0h
Bit Access
RWC
RWC
RWC
RWC
RWC
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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