EP80579 Datasheet, PDF (1497/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
37.6.5.6
TDLEN – Transmit Descriptor Length Register
This register contains the descriptor length and must be 128B aligned (i.e. the lower 7
bits are always 0).
Table 37-72. TDLEN: Transmit Descriptor Length Register
Description:
View: PCI 1
BAR: CSRBAR
Bus:Device:Function: M:0:0
Offset Start: 3808h
Offset End: 380Bh
View: PCI 2
BAR: CSRBAR
Bus:Device:Function: M:1:0
Offset Start: 3808h
Offset End: 380Bh
View: PCI 3
BAR: CSRBAR
Bus:Device:Function: M:2:0
Offset Start: 3808h
Offset End: 380Bh
Size: 32 bits
Default: 00000000h
GbE0: Core
Power Well: Gbe1/2:
Core
Bit Range Bit Acronym
Bit Description
31 : 20
19 : 07
06 : 00
Rsvd
LEN
0
Reserved
Descriptor Length
Writes are ignored, reads return 0.
Sticky
Bit Reset
Value
0h
0h
0h
Bit Access
RV
RW
RV
37.6.5.7
TDH – Transmit Descriptor Head Register
This register contains the head pointer for the transmit descriptor ring. It points to a
16B datum. Hardware controls this pointer. The only time that software should write to
this register is after a reset (hardware reset or CTRL.RST) and before enabling the
transmit function (TCTL.EN). Writing this register while the transmit function is enabled
will cause indeterminate behavior.
Table 37-73. TDH: Transmit Descriptor Head Register
Description:
View: PCI 1
BAR: CSRBAR
Bus:Device:Function: M:0:0
Offset Start: 3810h
Offset End: 3813h
View: PCI 2
BAR: CSRBAR
Bus:Device:Function: M:1:0
Offset Start: 3810h
Offset End: 3813h
View: PCI 3
BAR: CSRBAR
Bus:Device:Function: M:2:0
Offset Start: 3810h
Offset End: 3813h
Size: 32 bits
Default: 00000000h
GbE0: Core
Power Well: Gbe1/2:
Core
Bit Range Bit Acronym
Bit Description
31 : 16
15 : 00
Rsvd
TDH
Reserved
Transmit Descriptor Head
Sticky
Bit Reset
Value
0h
0h
Bit Access
RV
RW
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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