EP80579 Datasheet, PDF (209/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
7.3.8
Root Complex: Bus 0, Device 31, Function 0
The Root Complex includes the registers listed in Table 7-21. These registers
materialize in memory space (via PCI memory BAR), respectively. See Chapter 17.0,
“Bridging and Configuration” for detailed discussion of these registers.
Table 7-21. Bus 0, Device 31, Function 0: Summary of Root Complex Configuration
Registers Mapped Through RCBA Memory BAR
Offset Start Offset End
Register ID - Description
Default
Value
0000h
0004h
0008h
000Ch
000Eh
0010h
0014h
001Ah
0100h
0104h
0110h
0118h
01A0h
01A4h
01A8h
01AAh
3108h
3140h
3144h
31FFh
3400h
3404h
3410h
3414h
3418h
341Ch
0003h
0007h
000Bh
000Dh
000Fh
0013h
0017h
001Bh
0103h
0107h
0113h
011Fh
01A3h
01A7h
01A9h
01ABh
310Bh
3141h
3145h
31FFh
3403h
3407h
3413h
3417h
341Bh
341Fh
“Offset 0000h: VCH - Virtual Channel Capability Header Register” on page 691
10010002h
“Offset 0004h: VCAP1 - Virtual Channel Capability 1 Register” on page 691
0801h
“Offset 0008h: VCAP2 - Virtual Channel Capability 2 Register” on page 692
0001h
“Offset 000Ch: PVC - Port Virtual Channel Control Register” on page 692
0h
“Offset 000Eh: PVS -Port Virtual Channel Status Register” on page 693
0h
“Offset 0010h: V0CAP - Virtual Channel 0 Resource Capability Register” on
page 693
00000001h
“Offset 0014h: V0CTL - Virtual Channel 0 Resource Control Register” on page 694 800000FFh
“Offset 001Ah: V0STS - Virtual Channel 0 Resource Status Register” on page 695 0h
“Offset 0100h: RCTCL - Root Complex Topology Capabilities List Register” on
page 696
1A010005h
“Offset 0104h: ESD - Element Self Description Register” on page 696
00000102h
“Offset 0110h: ULD - Upstream Link Description Register” on page 697
0001h
“Offset 0118h: ULBA - Upstream Link Base Address Register” on page 697
00000000000
00000h
“Offset 01A0h: ILCL - Internal Link Capabilities List Register” on page 698
00010006h
“Offset 01A4h: LCAP - Link Capabilities Register” on page 698
0012441h
“Offset 01A8h: LCTL - Link Control Register” on page 699
0h
“Offset 01AAh: LSTS - Link Status Register” on page 700
0041h
“Offset 3108h: D29IP - Device 29 Interrupt Pin Register” on page 702
10004321h
“Offset 3140h: D31IR - Device 31 Interrupt Route Register” on page 702
3210h
“Offset 3144h: D29IR - Device 29 Interrupt Route Register” on page 703
3210h
“Offset 31FFh: OIC - Other Interrupt Control Register” on page 704
0h
“Offset 3400h: RC - RTC Configuration Register” on page 704
0h
“Offset 3404h: HPTC - High Performance Precision Timer Configuration Register”
on page 705
0h
“Offset 3410h: GCS - General Control and Status Register” on page 706
Variable
“Offset 3414h: BUC - Backed Up Control Register” on page 708
Variable
“Offset 3418h: FD - Function Disable Register” on page 709
00000080h
“Offset 341Ch: PRC - Power Reduction Control Register Clock Gating” on page 711 0h
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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