EP80579 Datasheet, PDF (38/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Contents
35.11.1.30 Offset F8h: MDATA – Message Signalled Interrupt Data Register.......... 1318
35.12 Expansion Bus Configuration Space: Bus M, Device 8, Function 0 ........................ 1319
35.12.1 Register Details .................................................................................... 1319
35.12.1.1 Offset 00h: VID – Vendor Identification Register................................ 1320
35.12.1.2 Offset 02h: DID – Device Identification Register ................................ 1320
35.12.1.3 Offset 04h: PCICMD – Device Command Register .............................. 1321
35.12.1.4 Offset 06h: PCISTS – Device Status Register .................................... 1321
35.12.1.5 Offset 08h: RID – Revision ID Register............................................. 1322
35.12.1.6 Offset 09h: CC – Class Code Register............................................... 1323
35.12.1.7 Offset 0Eh: HDR – Header Type Register .......................................... 1323
35.12.1.8 Offset 10h: CSRBAR – Control and Status Registers Base
Address Register ........................................................................... 1323
35.12.1.9 Offset 14h: MMBAR – Expansion Bus Base Address Register................ 1324
35.12.1.10 Offset 2Ch: SVID – Subsystem Vendor ID Register ............................ 1325
35.12.1.11 Offset 2Eh: SID – Subsystem ID Register ......................................... 1325
35.12.1.12 Offset 34h: CP – Capabilities Pointer Register.................................... 1326
35.12.1.13 Offset 3Ch: IRQL – Interrupt Line Register........................................ 1326
35.12.1.14 Offset 3Dh: IRQP – Interrupt Pin Register......................................... 1327
35.12.1.15 Offset 40h: LEBCTL – LEB Control Register ....................................... 1327
35.12.1.16 Offset DCh: PCID – Power Management Capability ID Register ............ 1327
35.12.1.17 Offset DDh: PCP – Power Management Next Capability Pointer
Register ....................................................................................... 1328
35.12.1.18 Offset DEh: PMCAP – Power Management Capability Register .............. 1328
35.12.1.19 Offset E0h: PMCS – Power Management Control and Status
Register ....................................................................................... 1329
35.12.1.20 Offset E4h: SCID – Signal Target Capability ID Register ..................... 1329
35.12.1.21 Offset E5h: SCP – Signal Target Next Capability Pointer Register ......... 1330
35.12.1.22 Offset E6h: SBC – Signal Target Byte Count Register ......................... 1330
35.12.1.23 Offset E7h: STYP – Signal Target Capability Type Register .................. 1330
35.12.1.24 Offset E8h: SMIA – Signal Target IA Mask Register ............................ 1331
35.12.1.25 Offset E9h: Reserved Register......................................................... 1331
35.12.1.26 Offset EAh: Reserved Register ........................................................ 1331
35.12.1.27 Offset ECh: SINT – Signal Target Raw Interrupt Register .................... 1331
35.12.1.28 Offset F0h: MCID – Message Signalled Interrupt Capability ID
Register ....................................................................................... 1332
35.12.1.29 Offset F1h: MCP – Message Signalled Interrupt Next Capability Pointer
Register ....................................................................................... 1332
35.12.1.30 Offset F2h: MCTL – Message Signalled Interrupt Control
Register ....................................................................................... 1333
35.12.1.31 Offset F4h: MADR – Message Signalled Interrupt Address
Register ....................................................................................... 1333
35.12.1.32 Offset F8h: MDATA – Message Signalled Interrupt Data Register.......... 1334
36.0 AIOC Interfaces ................................................................................................... 1335
36.1 Overview ...................................................................................................... 1335
36.2 Gigabit Ethernet (GbE) ................................................................................... 1335
36.2.1 Integrated DMA Features ....................................................................... 1336
36.2.2 MAC Features....................................................................................... 1336
36.2.3 Host Off-Loading Features ..................................................................... 1337
36.2.4 Interfaces............................................................................................ 1337
36.2.5 Power Management .............................................................................. 1337
36.2.6 Serial EEPROM Interface ........................................................................ 1338
36.3 Local Expansion Bus Interface (LEB)................................................................. 1338
36.4 Serial Synchronous Port (SSP)......................................................................... 1339
36.5 Controller Area Network (CAN) ........................................................................ 1339
36.6 IEEE 1588 Time Synchronization Hardware Assist ............................................. 1340
37.0 Gigabit Ethernet Controller .................................................................................. 1341
37.1 Overview ...................................................................................................... 1341
Intel^® EP80579 Integrated Processor Product Line Datasheet
38
August 2009
Order Number: 320066-003US