EP80579 Datasheet, PDF (1203/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
33.7
33.7.1
Serial IRQ
The SIW supports the serial interrupt to transmit interrupt information to the host
system. The serial interrupt scheme adheres to the Serial IRQ Specification.
Timing Diagrams For SIW_SERIRQ Cycle
Figure 33-3. Start Frame Timing with Source Sampled a Low Pulse on IRQ1
Notes:
1.
H=Host Control; R=Recovery; T=Turn-Around; SL=Slave Control; S=Sample
2.
Start Frame pulse can be 4-8 clocks wide depending on the location of the device in the PCI bridge
hierarchy in a synchronous bridge design.
Figure 33-4. Stop Frame Timing with Host Using Quiet Mode Sampling Period
33.7.1.1
Notes:
1.
H=Host Control; R=Recovery; T=Turn-Around; S=Sample; I=Idle
2.
Stop pulse is two clocks wide for Quiet mode, three clocks wide for Continuous mode.
3.
There may be none, one or more Idle states during the Stop Frame.
4.
The next SIW_SERIRQ cycle’s Start Frame pulse may or may not start immediately after the turn-
around clock of the Stop Frame.
SIW_SERIRQ Cycle Control
There are two modes of operation for the SIW_SERIRQ Start Frame.
1. Quiet (Active) Mode: Any device may initiate a Start Frame by driving the
SIW_SERIRQ low for one clock, while the SIW_SERIRQ is Idle. After driving low for
one clock the SIW_SERIRQ is immediately tri-stated without at any time driving
high. A Start Frame may not be initiated while the SIW_SERIRQ is Active. The
SIW_SERIRQ is Idle between Stop and Start Frames. The SIW_SERIRQ is Active
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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