EP80579 Datasheet, PDF (1005/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 26-38. Offset 08h: HCCPARAMS - Host Controller Capability Parameters Register
(Sheet 2 of 2)
Description:
View: PCI
BAR: MBAR
Bus:Device:Function: 0:29:7
Offset Start: 08h
Offset End: 0Bh
Size: 32 bit
Default: 00006871h
Power Well: Core
Bit Range
02
01
00
Bit Acronym
Bit Description
Sticky
ASPC
PFLF
ADD_CAP
Asynchronous Schedule Park Capability: This bit is
hardwired to 0 indicating that the Host Controller does not
support this optional feature.
Programmable Frame List Flag:
0 = If this bit is set to a zero, then system software must
use a frame list length of 1024 elements with this
host controller. The USBCMD register Frame List Size
field is a read-only register and must be set to zero.
1 = If set to a one, then system software can specify and
use a smaller frame list and configure the host
controller via the USBCMD register Frame List Size
field. The frame list must always be aligned on a 4K
page boundary. This requirement ensures that the
frame list is always physically contiguous.
Different frame list lengths are not supported. This bit is
read-only ‘0’.
64-bit Addressing Capability: This field documents the
addressing range capability of this implementation. The
value of this field determines whether software must use
the 32-bit or 64-bit data structures. Values for this field
have the following interpretation:
0 = Data structures using 32-bit address memory
pointers
1 = Data structures using 64-bit address memory
pointers
Only 64-bit addressing is supported. This bit is read-only
‘1’.
Only 44 bits of addressing is supported. Bits 63:44 will
always be 0 on cycles generated to memory.
Bit Reset
Value
0h
0h
1h
Bit Access
RO
RO
RO
26.3.2
Host Controller Operational Register Details
This section defines the enhanced host controller operational registers. These registers
are located after the capabilities registers. The operational register base must be
DWord aligned and is calculated by adding the value in the first capabilities register to
the base address of the enhanced host controller register address space. In the
following text, the offset is relative to the Memory Base Register. All registers are
32 bits in length. Software must read and write these registers using only Dword
accesses.
These registers are divided into two sets. The first set at offsets 20h to 3Fh are
implemented in the core power well. Unless otherwise noted, the core-well registers
are reset by the assertion of any of the following:
• core well hardware reset
• HCRESET
• D3-to-D0 reset
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
1005