EP80579 Datasheet, PDF (1504/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 37-78. TSPMT: TCP Segmentation Pad And Minimum Threshold Register
Description:
View: PCI 1
BAR: CSRBAR
Bus:Device:Function: M:0:0
Offset Start: 3830h
Offset End: 3833h
View: PCI 2
BAR: CSRBAR
Bus:Device:Function: M:1:0
Offset Start: 3830h
Offset End: 3833h
View: PCI 3
BAR: CSRBAR
Bus:Device:Function: M:2:0
Offset Start: 3830h
Offset End: 3833h
Size: 32 bits
Default: 01000400h
GbE0: Core
Power Well: Gbe1/2:
Core
Bit Range
31 : 16
15 : 00
Bit Acronym
Bit Description
Sticky
TSPBP
TSMT
TCP Segmentation Packet Buffer Padding, value is in
bytes. This field allows software configuration of packet
buffer space which must be reserved as “pad” for worst-
case header insertion. To ensure that this value does not
prevent descriptors from being serviced at all, it is
necessary that the transmit packet buffer allocation should
be larger than the sum of (maximum TCP HDRLEN +
maximum MSS + TSPMT.TMPBP + 80 bytes).
TCP Segmentation Minimum Transfer, value is in bytes.
The DMA will attempt to issue burst fetches for as much
data as possible, and it is possible for the transmit DMA to
cause the transmit packet buffer to approach fullness (less
the pad specified). However, if the packet buffer empties
slightly, the transmit DMA could initiate a series of small
transfers.
To further optimize the efficiency of the transmit DMA
during TCP segmentation operation, the this TSPMT.TSMT
field allows software configuration of the minimum number
of bytes which the DMA should attempt to transfer in a
single burst operation. The transmit DMA will use this value
to refrain from issuing a burst read until at least
TSPMT.TSMT bytes of data from the current data descriptor
can be stored in the packet buffer.
This check will be ignored if, after a series of DMA
operations, the descriptor contains a smaller number of
unfetched data bytes. To ensure that this minimum
threshold does not prevent descriptors from being serviced
at all, it is necessary that the transmit packet buffer
allocation should be larger than the sum of (TSPMT.TSMT +
TSPMT.TSPBP + 80 bytes).
Bit Reset
Value
0x0100h
0x0400h
Bit Access
RW
RW
Intel^® EP80579 Integrated Processor Product Line Datasheet
1504
August 2009
Order Number: 320066-003US