EP80579 Datasheet, PDF (58/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Contents
7-49
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7-53
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7-55
7-56
7-57
7-58
7-59
7-60
7-61
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7-64
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7-67
8-1
9-1
10-1
10-2
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10-4
10-5
10-6
10-7
10-8
10-9
10-10
10-11
10-12
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10-16
10-17
10-18
10-19
11-1
11-2
11-3
11-4
11-5
Bus M, Device2, Function 0: Summary of Gigabit Ethernet MAC Interface PCI Configuration
Registers ......................................................................................................... 228
Bus M, Device 0, Function 0: Gigabit Ethernet MAC I/O Spaces Registers ................. 229
Bus M, Device 1, Function 0: Gigabit Ethernet MAC I/O Spaces Registers ................. 229
Bus M, Device 2, Function 0: Gigabit Ethernet MAC I/O Spaces Registers ................. 229
Bus M, Device 0, Function 0: Summary of Gigabit Ethernet Interface Registers Mapped
Through CSRBAR Memory BAR ........................................................................... 229
Bus M, Device 1, Function 0: Summary of Gigabit Ethernet Interface Registers Mapped
Through CSRBAR Memory BAR ........................................................................... 233
Bus M, Devices 2, Function 0: Summary of Gigabit Ethernet Interface Registers Mapped
Through CSRBAR Memory BAR ........................................................................... 236
Bus M, Device 3, Function 0: Summary of GCU PCI Configuration Registers .............. 240
Bus M, Device 3, Function 0: Summary of GCU Registers Mapped Through CSRBAR
Memory BAR .................................................................................................... 240
Bus M, Device 4, Function 0: Summary of CAN Interface PCI Configuration Registers. 242
Bus M, Devices 5, Function 0: Summary of CAN Interface PCI Configuration Registers243
Bus M, Device 4, Function 0: Summary of CAN Registers Mapped Through CSRBAR
Memory BAR .................................................................................................... 244
Bus M, Device 5, Function 0: Summary of CAN Registers Mapped Through CSRBAR
Memory BAR .................................................................................................... 244
Bus M, Device 6, Function 0: Summary of SSP Controller PCI Configuration Registers 245
Bus M, Device 6, Function 0: Summary of SSP CSRs ............................................. 246
Bus M, Device 7, Function 0: Summary of IEEE 1588 Timestamp Unit PCI Configuration
Registers ......................................................................................................... 247
Bus M, Device 7, Function 0: Summary of IEEE 1588 TSYNC CSRs .......................... 248
Bus M, Device 8, Function 0: Summary of Local Expansion Bus PCI Configuration
Registers ......................................................................................................... 249
Bus M, Device 8, Function 0: Summary of Local Expansion Bus Registers Mapped Through
CSRBAR PCI Memory BAR"................................................................................. 250
Processor Version Identification Signature (CPUID) ............................................... 254
Supported PCI Express Configurations ................................................................ 257
Regions of Memory Ranges ................................................................................ 267
System Memory Space ...................................................................................... 268
IMCH VGA and MDA Memory Spaces ................................................................... 268
IMCH PAM Memory Address Ranges .................................................................... 270
PAM Associated Attribute Bits ............................................................................ 273
TSEG SMM Memory Space ................................................................................. 274
PCI Express Enhanced Configuration Aperture ...................................................... 274
IOAPIC Memory Space ...................................................................................... 275
FSB Interrupt Memory Space.............................................................................. 275
High SMM Memory Space................................................................................... 276
Device 2 Memory and Prefetchable Memory.......................................................... 277
Device 3 Memory and Prefetchable Memory.......................................................... 277
Device 4 Memory and Prefetchable Memory.......................................................... 277
EDMA Accesses to Fixed Address Spaces ............................................................. 278
EDMA Accesses to Relocatable Address Spaces ..................................................... 279
Supported SMM Ranges ..................................................................................... 282
Fixed I/O Ranges Decoded by IICH .................................................................... 284
Variable I/O Decode Ranges .............................................................................. 286
IICH Memory Decode Ranges (from IA-32 core Perspective) .................................. 287
Supported DDR2 Device Densities and Width........................................................ 291
Supported DRAM Capacity for 64b Mode .............................................................. 291
Supported DRAM Capacity for 32b Mode .............................................................. 292
Raw Cards Supported by the EP80579 ................................................................ 292
Supported DDR2 Data Speeds ............................................................................ 292
Intel^® EP80579 Integrated Processor Product Line Datasheet
58
August 2009
Order Number: 320066-003US