EP80579 Datasheet, PDF (812/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
22.2.1.5 Offset 2Ch: GPI_INV - GPIO Signal Invert Register
Table 22-8. Offset 2Ch: GPI_INV - GPIO Signal Invert Register
Description: This register allows GPIO inputs for GPIO pins 31-0 to be inverted.
View: PCI
Size: 32 bit
BAR: GBA(IO)
Default: 00000000h
Bus:Device:Function: 0:31:0
Offset Start: 2Ch
Offset End: 2Fh
Power Well: Core^a
Bit Range Bit Acronym
Bit Description
Sticky
31 :16
15 : 14
13 : 12
11 : 08
07 : 00
Reserved Reserved
Input Inversion: These bits only have effect if the
corresponding GPIO is used as an input. This is used to
allow active-low and active-high inputs to cause SMI#
or SCI.
0 = No bit is inverted.
1 = The corresponding data value in the GP_LVL bit is
inverted.
GPI_INV_15_14
These bits correspond to GPI in the resume well and are
reset to their native function by RSMRST# or a write to
the CF9h register or any other PLTRST#.
For triggering requirements, see Section 22.3.2,
“Triggering” on page 815.
The setting of these bits have no effect if the
corresponding GPIO is programmed as an output.
Input Inversion: These bits only has effect if the
corresponding GPIO is used as an input. This is used to
allow active-low and active-high inputs to cause SMI#
or SCI.
GPI_INV_13_12 ^{0 = No bit is inverted.}
1 = The corresponding data value in the GP_LVL bit is
inverted.
These bits correspond to GPI in the core well and are
reset to their native function by RSMRST#.
Input Inversion: These bits only have effect if the
corresponding GPIO is used as an input. This is used to
allow active-low and active-high inputs to cause SMI#
or SCI.
0 = No bit is inverted.
1 = The corresponding data value in the GP_LVL bit is
inverted.
GPI_INV_11_8
These bits correspond to GPI in the resume well and are
reset to their native function by RSMRST# or a write to
the CF9h register or any other PLTRST#.
For triggering requirements, see Section 22.3.2,
“Triggering” on page 815.
The setting of these bits have no effect if the
corresponding GPIO is programmed as an output.
GPI_INV_7_0
Input Inversion: This bit only has effect if the
corresponding GPIO is used as an input. This is used to
allow active-low and active-high inputs to cause SMI#
or SCI.
0 = No bit is inverted.
1 = The corresponding data value in the GP_LVL bit is
inverted.
These bits correspond to GPI in the core well and are
reset to their native function by PLTRST#.
a. Core for 0:7, 16:21, 23; Resume for 8:15, 24:31.
Bit Reset
Value
00h
00b
00b
0h
00h
Bit Access
RO
RW
RW
RW
RW
Intel^® EP80579 Integrated Processor Product Line Datasheet
812
August 2009
Order Number: 320066-003US