EP80579 Datasheet, PDF (1658/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
41.6.1.18 Offset 0044h: TS_CH_EVENT[0-7] - Time Synchronization Channel
Event Register (Per Ethernet Channel)
Register
Name
TS_Ch_Event
Access
(See below.) Reset Value x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
*Address offsets per channel…
Channel 0 = 0x044
Channel 1 = 0x064
Channel 2 = 0x084
Channel 3 = 0x0A4
Channel 4 = 0x0C4
Channel 5 = 0x0E4
Channel 6 = 0x104
Channel 7 = 0x124
Table 41-28. Offset 0044h: TS_CH_EVENT[0-7] - Time Synchronization Channel Event
Register Per Ethernet Channel)
Description:
View: PCI
BAR: CSRBAR
Bus:Device:Function: M:7:0
0044h at
Offset Start: 20h
Offset End: 0047h at
20h
Size: 32 bits
Default: 0000h
Power Well: Core
Bit Range
31 : 2
1: 1
0: 0
Bit Acronym
Bit Description
Sticky
Reserved
rxs
txs
Reserved for future use.
Receive Snapshot Locked. This bit is automatically set
when a Delay_Req message in Master mode, or a Sync
message in Slave mode, is received and the ta bit in the
corresponding TS_Channel_Control register is clear. It
indicates that the current system time value has been
captured in the RECV_Snapshot register and that further
changes to the RECV_Snapshot are now locked out. To
clear this bit, write a ‘1’ to it.
Transmit Snapshot Locked. This bit is automatically set
when a Sync message in Master mode, or a Delay_Req
message in Slave mode, is transmitted and the ta bit in
the corresponding TS_Channel_Control register is clear. It
indicates that the current system time value has been
captured in the XMIT_Snapshot register and that further
changes to the XMIT_Snapshot are now locked out. To
clear this bit, write a ‘1’ to it.
Bit Reset
Value
0h
0h
0h
Bit Access
RV
RWC
RWC
Intel^® EP80579 Integrated Processor Product Line Datasheet
1658
August 2009
Order Number: 320066-003US