EP80579 Datasheet, PDF (36/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Contents
35.8.1.15 Offset E0h: PMCS – Power Management Control and Status
Register ....................................................................................... 1272
35.9 CAN Controller Configuration Spaces: Bus M, Device 4-5, Function 0 .................... 1273
35.9.1 Register Details .................................................................................... 1273
35.9.1.1 Offset 00h: VID – Vendor Identification Register................................ 1275
35.9.1.2 Offset 02h: DID – Device Identification Register ................................ 1275
35.9.1.3 Offset 02h: DID – Device Identification Register ................................ 1276
35.9.1.4 Offset 04h: PCICMD – Device Command Register .............................. 1276
35.9.1.5 Offset 06h: PCISTS – Device Status Register .................................... 1277
35.9.1.6 Offset 08h: RID – Revision ID Register............................................. 1278
35.9.1.7 Offset 09h: CC – Class Code Register............................................... 1278
35.9.1.8 Offset 0Eh: HDR – Header Type Register .......................................... 1279
35.9.1.9 Offset 10h: CSRBAR – Control and Status Registers Base
Address Register ........................................................................... 1279
35.9.1.10 Offset 2Ch: SVID – Subsystem Vendor ID Register ............................ 1280
35.9.1.11 Offset 2Eh: SID – Subsystem ID Register ......................................... 1280
35.9.1.12 Offset 34h: CP – Capabilities Pointer Register.................................... 1281
35.9.1.13 Offset 3Ch: IRQL – Interrupt Line Register........................................ 1281
35.9.1.14 Offset 3Dh: IRQP – Interrupt Pin Register......................................... 1282
35.9.1.15 Offset 40h: CANCTL – CAN Control Register ...................................... 1282
35.9.1.16 Offset DCh: PCID – Power Management Capability ID Register ............ 1283
35.9.1.17 Offset DDh: PCP – Power Management Next Capability Pointer
Register ....................................................................................... 1283
35.9.1.18 Offset DEh: PMCAP – Power Management Capability Register .............. 1284
35.9.1.19 Offset E0h: PMCS – Power Management Control and Status
Register ....................................................................................... 1284
35.9.1.20 Offset E4h: SCID – Signal Target Capability ID Register ..................... 1285
35.9.1.21 Offset E5h: SCP – Signal Target Next Capability Pointer Register ......... 1285
35.9.1.22 Offset E6h: SBC – Signal Target Byte Count Register ......................... 1286
35.9.1.23 Offset E7h: STYP – Signal Target Capability Type Register .................. 1286
35.9.1.24 Offset E8h: SMIA – Signal Target IA Mask Register ............................ 1287
35.9.1.25 Offset E9h: Reserved Register......................................................... 1287
35.9.1.26 Offset EAh: Reserved Register ........................................................ 1287
35.9.1.27 Offset ECh: SINT – Signal Target Raw Interrupt Register .................... 1287
35.9.1.28 Offset F0h: MCID – Message Signalled Interrupt Capability ID
Register ....................................................................................... 1288
35.9.1.29 Offset F1h: MCP – Message Signalled Interrupt Next Capability Pointer
Register ....................................................................................... 1288
35.9.1.30 Offset F2h: MCTL – Message Signalled Interrupt Control Register......... 1289
35.9.1.31 Offset F4h: MADR – Message Signalled Interrupt Address
Register ....................................................................................... 1289
35.9.1.32 Offset F8h: MDATA – Message Signalled Interrupt Data Register.......... 1290
35.10 SSP Controller Configuration Space: Bus M, Device 6, Function 0 ........................ 1291
35.10.1 Register Details .................................................................................... 1291
35.10.1.1 Offset 00h: VID – Vendor Identification Register................................ 1292
35.10.1.2 Offset 02h: DID – Device Identification Register ................................ 1292
35.10.1.3 Offset 04h: PCICMD – Device Command Register .............................. 1292
35.10.1.4 Offset 06h: PCISTS – Device Status Register .................................... 1293
35.10.1.5 Offset 08h: RID – Revision ID Register............................................. 1294
35.10.1.6 Offset 09h: CC – Class Code Register............................................... 1295
35.10.1.7 Offset 0Eh: HDR – Header Type Register .......................................... 1295
35.10.1.8 Offset 10h: CSRBAR – Control and Status Registers Base
Address Register ........................................................................... 1295
35.10.1.9 Offset 2Ch: SVID – Subsystem Vendor ID Register ............................ 1296
35.10.1.10 Offset 2Eh: SID – Subsystem ID Register ......................................... 1296
35.10.1.11 Offset 34h: CP – Capabilities Pointer Register.................................... 1297
35.10.1.12 Offset 3Ch: IRQL – Interrupt Line Register........................................ 1297
35.10.1.13 Offset 3Dh: IRQP – Interrupt Pin Register......................................... 1298
35.10.1.14 Offset DCh: PCID – Power Management Capability ID Register ............ 1298
Intel^® EP80579 Integrated Processor Product Line Datasheet
36
August 2009
Order Number: 320066-003US