EP80579 Datasheet, PDF (1133/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
30.3.2.1
30.3.2.2
30.3.2.3
30.3.2.4
30.3.2.5
30.3.2.6
Front Side Bus Interrupt Delivery
The IICH requires that the I/O APIC deliver interrupt messages to the processor in a
parallel manner, rather than using the I/O APIC serial scheme.
Delivery of interrupts is completed by the IICH writing to a memory location that is
snooped by the processor. The processors snoops the cycle to know which interrupt
goes active.
The following sequence is used:
1. When the IICH detects an interrupt event (active edge for edge-triggered mode or
a change for level-triggered mode), it sets or resets the internal IRR bit associated
with that interrupt.
2. Internally, the IICH requests to use the bus in a way that automatically flushes
upstream buffers. This can be internally implemented similar to a DMA device
request.
3. The IICH delivers the message by performing a write cycle to the appropriate
address with the appropriate data. The address and data formats are described in
Section 30.3.2.6, “Interrupt Message Format” on page 1133.
Edge-Triggered Operation
In this case, the “Assert Message” is sent when there is an inactive-to-active edge on
the interrupt.
Level-Triggered Operation
In this case, the “Assert Message” is sent when there is an inactive-to-active edge on
the interrupt. If after the EOI the interrupt is still active, then another “Assert Message”
is sent to indicate that the interrupt is still active.
Registers Associated with Front-Side Bus Interrupt Delivery
Capabilities Indication is the capability to support front-side bus interrupt delivery
indicated via ACPI configuration techniques. This involves the BIOS creating a data
structure that gets reported to the ACPI configuration software.
EOI
The mechanism by which the processor may generate an EOI is PCI Express* EOI
message.
The PCI Express* EOI message is used by IA-32 core. It is broadcast to the internal
IOxAPIC. The data of the EOI message is the vector. This value is compared with all the
vectors inside the IOxAPIC, and any match causes RTE[x].RIRR to be cleared. See
Section 17.1.6.1 for a description of the EOI vendor-specific message.
Interrupt Message Format
CMI writes the interrupt message internally as a 32-bit memory write cycle. It uses the
following formats shown in Table 30-18 and Table 30-19 for the address and data.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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