EP80579 Datasheet, PDF (1667/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
41.6.1.27 Offset 0148h: TS_CANSnapHi[0-1] - Transmit Snapshot High Register
(Per CAN Channel)
Register
Name
TS_CANSnapHi
Access
(See below.) Reset Value 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CAN_Snapshot_High[31:0]
*Address offsets per channel…
CAN Channel 0 = 0x148
CAN Channel 1 = 0x158
Table 41-37. Offset 0148h: TS_CANSnapHi[0-1] - Transmit Snapshot High Register (Per
CAN Channel)
Description:
View: PCI
BAR: CSRBAR
Bus:Device:Function: M:7:0
0148h at
Offset Start: 10h
Offset End: 014Bh at
10h
Size: 32 bits
Default: 0000h
Power Well: Core
Bit Range
31 : 00
Bit Acronym
Bit Description
Sticky
CAN_
Snapshot_
High
When a CAN packet is transmitted or received, the current
system time is captured in this CAN_Snapshot register.
• The CAN_Snapshot_Low register contains the lower
32 bits of the time value.
• The CAN_Snapshot_High register contains the upper
32 bits.
After a CAN_Snapshot has occurred, the valid indication
in the TS_CAN_Status register does not clear until the
user writes a ‘1’ to that bit in that register.
The firmware should check the state of the valid bit in the
CAN_Status register before reading CAN_Snapshot_Low.
Because the snapshot value could change between reads
of the Low and High snapshot registers, the firmware
should check the state of the overrun bit before and after
the read of the CAN_Snapshot_High register. After reading
the CAN_Snapshot_High register, the firmware should
write a '1' to the valid bit and the overrun bit if applicable.
Bit Reset
Value
0000h
Bit Access
RO
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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