EP80579 Datasheet, PDF (1554/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
37.7.4.2 Transition from D0a to D3 and Back without Reset
Figure 37-53.Transition from D0a to D3 and Back without Reset
CLK
RESET
Reading EEPROM
D3 write
1
Wakeup Enabled
DState D0a
D0 Write
2
3
td0ee
tee
td0mem
6
Memory Access Enable ⁷
Read EEPROM
Any mode
D3
4
APM
11
D0u
D0
Note
1
2
4
6
10
11
Writing a 11 to the Power State field of the Power Management Control/Status Register (PMCSR)
will transition the power state to D3.
The system can delay an arbitrary amount of time between setting D3 mode and asserting RESET.
Upon assertion of RESET the MAC will go to “Dr” state.
The deassertion edge of RESET will case the EEPROM to be re-read and Wake Up disabled.
The system can delay an arbitrary time before enabling memory access.
Writing a 1 to the Memory Access Enable bit in the PCI Command Register will transition the MAC
from D0u to D0 state
Intel^® EP80579 Integrated Processor Product Line Datasheet
1554
August 2009
Order Number: 320066-003US