EP80579 Datasheet, PDF (305/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 11-17. Poisoning Granularity
Command
Read from DRAM
Read from DRAM
Error Source
DRAM
(DED)
DRAM
(DED)
Command Source
Memory Controller Action
IMCH
Poison parity bits on 32B granularity and
return read data to IMCH.
AIOC MT
Poison parity bits on 8B granularity and return
read data to AIOC memory target (MT).
Write to DRAM
IA or IO Device
including AIOC
(Parity Error)
IMCH
Poison ECC bits on 16B granularity and write
to DRAM.
Write to DRAM
AIOC
(Parity Error)
AIOC MT
Poison ECC bits on 8B granularity and write to
DRAM.
• ECC can be enabled by setting the DDIM bit in Section 16.1.1.43, “Offset 7Ch: DRC – DRAM Controller
Mode Register”.
• Poisoning of write data to DRAM can be enabled using the MEMPEN bit in Section 16.1.1.44, “Offset 84h:
ECCDIAG – ECC Detection/Correction Diagnostic Register”.
• Poisoning of read data from DRAM to IMCH or AIOC MT can be enabled by using ENDP bit in Section
16.1.1.43, “Offset 7Ch: DRC – DRAM Controller Mode Register”.
For compatibility with accepted IA platform algorithms and mechanisms, the memory
controller will follow general IA error logging and reporting mechanisms as closely as
possible with the following exception:
• The memory controller does not implement uncorrectable retries (DED retries).
Therefore all registers and bit definitions that support uncorrectable retries are not
implemented in the memory controller.
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August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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