EP80579 Datasheet, PDF (351/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Figure 13-3. NSI Type 1 Configuration Address Translation
CONFIG_ADDRESS
31
24 23
16 15
11 10 8 7
210
1
Reserved
Bus Number
Device Number Function Register Number x x
NSI Type 1 Configuration Address Extension
31
28 27
24 23
16 15
11 10 8 7
210
Reserved
Bus Number
Device Number Function Register Number 0 1
13.3.4 IMCH PCI Express Bus Configuration Mechanism
From the configuration perspective, the PCI Express ports are seen as PCI bus
interfaces residing on a Secondary Bus side of the “virtual” PCI-to-PCI bridges referred
to as the IMCH Host-PCI Express bridge. On the Primary bus side, the “virtual” PCI-to-
PCI bridge is attached to PCI Bus #0. Therefore the PRIMARY BUS NUMBER register is
hardwired to “0”. The “virtual” PCI-PCI bridge entity converts Type #1 PCI Bus
Configuration cycles on PCI Bus #0 into Type 0 or Type 1 configuration cycles on the
PCI Express interfaces. Type 1 configuration cycles on PCI Bus #0 that have a BUS
NUMBER that matches the SECONDARY BUS NUMBER of one of the IMCH’s “virtual” P2P
bridges are translated into Type 0 configuration cycles on the appropriate PCI Express
interface. The address bits are mapped as described in Figure 13-3.
If the Bus Number is non-zero, greater than the value programmed into the
SECONDARY BUS NUMBER register, and less than or equal to the value programmed
into the corresponding SUBORDINATE BUS NUMBER register the configuration cycle is
targeting a PCI bus downstream of the targeted PCI Express interface. The IMCH will
generate a Type 1 configuration cycle on the appropriate PCI Express interface. The
address bits are mapped as described in Figure 13-4.
Figure 13-4. Mechanism #1 Type 1 Configuration Address to PCI Address Mapping
3130
24 23
16 15
11 10
87
21 0
CONFIG_ADDRESS 1 Reserved Bus Number Device Number Function Number Reg. Index X X
PCI Address
AD(31:0)
1
3130
0
Bus Number Device Number Function Number Reg. Index 0 1
24 23
16 15
11 10
87
21 0
To prepare for mapping of the configuration cycles on PCI Express the initialization
software will go through the following sequence:
Scan all devices residing on the PCI Bus #0 using Type 0 configuration accesses.
For every device residing at bus #0 which implements PCI-to-PCI bridge functionality, it
will configure the secondary bus of the bridge with the appropriate number and scan
further down the hierarchy. This process will include the configuration of the “virtual”
PCI-to-PCI bridges within the IMCH used to map the PCI Express device’s address
spaces in a software specific manner.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
351