EP80579 Datasheet, PDF (167/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
6.1.3
EP80579 Power Sequencing and Reset Sequence
The following diagrams show the reset sequencing.
Figure 6-2. Reset Sequence
EP80579
3
Reference Clock
Stable (from
clock generator)
4
CRU
Clock
Stable
VRMPWRGD
Power Applied
to EP80579
1
CPU_VRD_PWR_GD
(from platform)
2
5
CPU_PWRGD
asserted
IICH
7
PLTRST#
de-asserted
IICH _IMCH
9
CPURST#
de-asserted
IMCH
10
Reset
Microcode
Execution
6
CPU
FSB and
Core
Clocks
Stable
PWROK
PWRGD
8
udrst
de-asserted
All the blocks
except the IA
CPU come out
of reset
Re-steer
to BIOS
CPU
DDR
Initialization
Memory Controller
Initialization
SYS_PWR_OK
(from platform)
5
1. The EP80579 receives power and drives its BSEL and V_SEL pins.
CPU_VRD_PWR_GD, SYS_PWR_OK (platform signals) are not asserted. PLTRST#,
and CPURST# (internal signal) are asserted.
2. CPU_VRD_PWR_GD is asserted (Platform signal). Internal signal name is
VRMPWRGD.
3. External Reference Clock provided from platform is stable, and is supplied to the
EP80579 internal PLLs to generate required internal clocks. Voltage regulator
output is modified to correspond to BSEL and V_SEL values.
4. The EP80579 CRU PLL locks.
5. SYS_PWR_OK (platform signal) == PWROK/PWRGD internal signal asserted
6. IO and Core PLLs lock on the CPU.
7. IICH de-asserts PLTRST#
8. IMCH de-asserts udrstb (internal reset unit). All EP80579 blocks except the IA-32
core come out of reset.
9. IMCH de-asserts CPURST# (internal signal) CPU executes the reset micro-code
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
167