EP80579 Datasheet, PDF (572/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
16.4.1.59 Offset 104h: UNCERRSTS - Uncorrectable Error Status Register
The Uncorrectable Error Status register reports the status of individual error sources on
the PCI Express* device. An individual error status bit that is set indicates that a
particular error occurred. Software may clear an error status bit by writing a ‘1’ to the
bit location. These bits are sticky through reset.
Table 16-198.Offset 104h: UNCERRSTS - Uncorrectable Error Status Register (Sheet 1 of
2)
Description:
View: PCI 1
BAR: Configuration
Bus:Device:Function: 0:2:0
Offset Start: 104h
Offset End: 107h
View: PCI 2
BAR: Configuration
Bus:Device:Function: 0:3:0
Offset Start: 104h
Offset End: 107h
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range Bit Acronym
Bit Description
Sticky
31 : 21
Reserved Reserved
Unsupported Request This error, if the first
uncorrectable error, loads the header log. This bit is sticky
20
USR_UNCERRS _{through reset.}
TS
0 = Cleared by writing a ‘1’ to the bit location.
Y
1 = Unsupported Request detected.
19
EES
ECRC Error Status.Note: ECRC is not supported for the
EP80579.
Y
Malformed TLP Status.This error, if the first
uncorrectable error, loads the header log. Malformed TLP
errors include: data payload length issues, byte enable rule
18
MTS
violations, and various other illegal field settings. This bit is _Y
sticky through reset.
0 = Cleared by writing a ‘1’ to the bit location.
1 = Malformed TLP detected
Receiver Overflow StatusOptional PCI Express*
specification bit, implemented for IMCH. This error, if the
first uncorrectable error, loads the header log. IMCH checks
for overflows on the following upstream queues: posted,
17
ROS
non-posted, and completion. This bit is sticky through
Y
reset.
0 = Cleared by writing a ‘1’ to the bit location.
1 = Receiver Overflow detected.
Unexpected Completion Status.This bit is set when the
device receives a completion which does not correspond to
any of the outstanding requests issued by that device. This
16
UCS
error, if the first uncorrectable error, loads the header log.
Y
This bit is sticky through reset.
0 = Cleared by writing a ‘1’ to the bit location.
1 = Unexpected Completion detected.
Completer Abort StatusOptional PCI Express*
specification bit, implemented for IMCH. If a request
received violates the specific programming model of this
device, but is otherwise legal, this bit is set. This error, if
15
CAS
the first uncorrectable error, load the header log. This bit is ^Y
sticky through reset.
0 = Cleared by writing a ‘1’ to the bit location.
1 = Completer Abort detected.
Completion Timeout StatusThe Completion Timeout
timer must expire if a Request is not completed in 50 ms,
but must not expire earlier than 50 µs. When the timer
14
CTS
expires, this bit is set. This bit is sticky through reset.
Y
0 = Cleared by writing a ‘1’ to the bit location.
1 = Completion timeout detected.
Bit Reset
Value
000h
0b
0b
0b
0b
0b
0b
0b
Bit Access
RWC
RO
RWC
RWC
RWC
RWC
RWC
Intel^® EP80579 Integrated Processor Product Line Datasheet
572
August 2009
Order Number: 320066-003US