EP80579 Datasheet, PDF (361/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
14.1.2.4
14.1.2.5
14.1.3
14.1.3.1
14.1.3.2
14.1.3.3
14.1.3.4
DRAM Refresh
As with any DRAM device, the storage element is inherently leaky, and must be
recharged periodically to avoid loss of data integrity. Circuitry in the memory
subsystem will ensure that refresh cycles occur in a periodic fashion across all active
DIMMS to meet the specific DRAM requirements.
DDR I/O Hardware Assisted Calibration
To determine read capture timing, hardware assisted calibration logic writes a pattern
into memory and then reads the data back with different hardware settings until the
optimum timing is found. Such calibration is described in the initialization walk-through
provided in the clocking and reset chapter of this document. Hardware provides the
capability to tune receive-enable timing, DQS centering within the received data eye
(both vertical and horizontal), output drive strength, and receive termination.
PCI Express Data Integrity
The PCI Express interfaces will incorporate several features to make this interface as
robust as possible without software intervention.
PCI Express Training
To establish a connection between PCI Express endpoints, they both participate in a
sequence of steps known as training. This sequence will establish the operational width
of the link as well as adjust skews of the various lanes within a link so that the data
sample points can correctly take a data sample off of the link. The x4 link pairs capable
of collapsing to x8 will first attempt to train independently, and will collapse to a single
link at the x8 width upon detection of a single device returning link ID information
upstream. Once the number of links has been established, they will negotiate to train
at the highest common width, and will step down in its supported link widths in order to
succeed in training. The ultimate result may be that the link has trained as a X1 link.
Although the bandwidth of this link size is substantially lower than a X8 link or even a
X4 link, it will allow communication between the two devices. Software will then be able
to interrogate the device at the other end of the link to determine why it failed to train
at a higher width, something that would not be possible without support for the X1 link
width. It should be noted that width negotiation is only done during training or
retraining, but not recovery.
PCI Express Retry
The PCI Express interface incorporates a link level retry mechanism. The hardware
detects when a transmission packet is corrupted and a retry of that particular packet
and all following packets will be performed. Although this will cause a temporary
interruption in the delivery of packets, it does so in order to maintain the link integrity.
PCI Express Recovery
When numerous errors occur, the hardware may determine that the quality of the
connection is in question, and the end points can enter a quick training sequence
known as recovery. The width of the connection will not be renegotiated, but the
adjustment of skew between lanes of the link may occur. This occurs without any
software intervention, but the software may be notified.
PCI Express Retrain
If the hardware is unable to perform a successful recovery then the link will
automatically revert to the polling state, and initiate a full retraining sequence. This is a
drastic event with an implicit reset to the downstream device and all subordinate
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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