EP80579 Datasheet, PDF (377/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Figure 15-1. Dword Configuration Read Protocol
DWORD Configuration Read Protocol (SMBus Block Write/Block Read, PEC Disabled)
SS
0110_000
WA
Cmd
=11000010
A
Byte Count
=4
A
Bus Number A
Device/
Function
A
Reg Number
[15:0]
A
Reg Number
[7:0]
CLOCK
STRETCH
A
P
SS
0110_000
WA
Cmd
=11000010
A
Sr
0110_000
RA
Byte Count
=5
A
Status
A Data[31:24] A Data[23:16] A Data[15:8] A Data[7:0] N P
B4518-01
Figure 15-2. Dword Configuration Write Protocol
DWORD Configuration Write Protocol (SMBus Block Write, PEC Disabled)
SS
0110_000
WA
Cmd
= 11001110
A
Byte Count
=8
A Bus Number A
Device/
Function
A
Reg Number
[15:8]
A
Reg Number
[7:0]
A
Data[31:24]
A
Data[23:16]
A Data[16:8] A Data[7:0]
CLOCK
STRETCH
AP
B4531-01
Figure 15-3. Dword Memory Read Protocol
DWORD Memory Read Protocol (SMBus Block Write/Block Read, PEC Disabled)
SS
0110_000
WA
Cmd
=11100010
A
Byte Count
=4
A
Destination
Memory
A
Add Offset
[23:16]
A
Add Offset
[15:8]
A
Add Offset
[7:0]
CLOCK
STRETCH
A
P
SS
0110_000
WA
Cmd
=11100010
A
SSr
0110_000
RA
Byte Count
=5
A
Status
A Data[31:24] A Data[23:16] A Data[15:8] A Data[7:0] N P
B4532-01
Figure 15-4. Dword Memory Write Protocol
DWORD Memory Write Protocol (SMBus Block Write, PEC Disabled)
S
0110_000
WA
Cmd
= 11101110
A
Byte Count
=8
A
Destination
Memory
A
Add Offset
[23:16]
A
Add Offset
[15:8]
A
Add Offset
[7:0]
A Data[31:24]
A
Data[23:16]
A Data[16:8] A
Data[7:0]
CLOCK
STRETCH
A
P
B4533-01
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
377