EP80579 Datasheet, PDF (1836/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
49.5.2
49.5.2.1
49.5.2.2
DDR2
The EP80579 provides an integrated memory controller for direct-connection to a single
channel of DDR2 with 400, 533, 640 and 800 MT/s unbuffered or registered memory
devices, with a maximum support of up to two ranks.
The electrical specifications of the EP80579’s DDR2 interface is compatible to the
JEDEC* Standard DDR2 SDRAM Specification, JESD79-2B, January 2005. The AC & DC
operating conditions are included in Chapter 5 of the JEDEC specification. Refer to the
subsections that follow for the electrical characteristics of the EP80579 DDR2 interface.
DDR2 Signal List
For DDR2 pin descriptions, refer to Table 48-8, “DDR2 Interface Signals” on page 1739.
DDR2 DC Characteristics
Table 49-13. DDR2 DC Input Characteristics
Signal
Group
Symbol
Parameter
Min
Nom
Max
Unit Notes
V_{IL (DC)}
Input Low Voltage (DC)
-
-
DDR_VREF -
150
mV
1, 2
DDR2
SSTL I/O
V_{IH (DC)}
Input High Voltage (DC)
DDR_VREF +
150
-
I _Leak
Input Leakage Current
(0<Vin<Vcc18)
-20
-
-
+20
mV
1, 2
μA
1
Notes:
1.
Refer to the JESD-79-2 and SSTL-18 Specification for further details.
2.
These input voltages apply only when the signals are inputs to the EP80579. When the signals are inputs to the SDRAM,
the SDRAM input voltage specifications apply.
Table 49-14. DDR2 DC Output Characteristics (Sheet 1 of 2)
Signal
Group
Symbol
Parameter
Min
Nom
Max
Unit Notes
DDR2
Output
I _OH
I _OL
V_OL
V_OH
Output High Current
Output Low Current
Output Low Voltage
Output High Voltage
-
-
0.0
DDR_VREF +
575
-
-11.0
mA
1, 2, 3
-
11.0
mA 1, 2, 3, 4
-
DDR_VREF -
575
mV
1, 2
-
-
mV
1, 2
C_Pin
Pin Capacitance
2.0
-
2.5
pF
1, 5
S_out
Output Slew Rate
2.2
-
3.2
V/ns 1, 6, 7
Notes:
1.
Refer to the JESD-79-2 and SSTL-18 Specification for further details.
2.
DDR2 DC parameters are specified with a 43 ohm test load to Vdd/2 and with up to 22 ohm resistive compensation
(RCOMP). Guaranteed by design. These values are typical values seen for this process, but not measured during
production testing
3.
I _OH=0mA at V_OH of 0.99*V_CC; I _OL=0mA at V_OL of 0.01*V_CC
4.
For open drain outputs, I _OL, MIN=3mA
5.
Guaranteed by design.
6.
Slew rate measured from vil(ac) to vih(ac)
7.
The absolute value of the slew rate as measured from DC to DC is equal to or greater than the slew rate as measured
from AC to AC. Guaranteed by design. These values are typical values seen for this process, but not measured during
production testing
Intel^® EP80579 Integrated Processor Product Line Datasheet
1836
August 2009
Order Number: 320066-003US