EP80579 Datasheet, PDF (1182/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
33.5.3.6
Offset 03h: LCR - Line Control Register
In the Line Control Register (LCR), the system programmer specifies the format of the
asynchronous data communications exchange. The serial data format consists of a start
bit (logic 0), five to eight data bits, an optional parity bit, and one or two stop bits
(logic 1). The LCR has bits for accessing the Divisor Latch and causing a break
condition. The programmer can also read the contents of the Line Control Register. The
read capability simplifies system programming and eliminates the need for separate
storage in system memory.
Table 33-18. Offset 03h: LCR - Line Control Register (Sheet 1 of 2)
Description:
View: IA F
Base Address: Base (IO)
Offset Start: 03h
Offset End: 03h
Size: 8 bit
Default: 00h
Power Well: Core
Bit Range
07
06
Bit Acronym
Bit Description
Sticky
DLAB
SB
Divisor register access bit: This bit is the Divisor
Latch Access Bit. It must be set high (logic 1) to access
the Divisor Latches of the Baud Rate Generator during a
READ or WRITE operation. It must be set low (logic 0)
to access the Receiver Buffer, the Transmit Holding
Register, or the Interrupt Enable Register.
0 = Access Transmit Holding register (THR), Receive
Buffer Register (RBR) and Interrupt Enable
Register.
1 = Access Divisor Latch Registers (DLL and DLH).
Set break: This bit is the set break control bit. It
causes a break condition to be transmitted to the
receiving UART. When SB is set to a logic 1, the serial
output (TXD) is forced to the spacing (logic 0) state and
remains there until SB is set to a logic 0. This bit acts
only on the TXD pin and has no effect on the transmitter
logic.
This feature enables the processor to alert a terminal in
a computer communications system. If the following
sequence is executed, no erroneous characters are
transmitted because of the break:
Load 00H in the Transmit Holding register in response to
a TDRQ interrupt
After TDRQ goes high (indicating that 00H is being
shifted out), set the break bit before the parity or stop
bits reach the TXD pin
Wait for the transmitter to be idle (TEMT = 1) and clear
the break bit when normal transmission has to be
restored
During the break, the transmitter can be used as a
character timer to accurately establish the break
duration. In FIFO mode, wait for the transmitter to be
idle (TEMT=1) to set and clear the break bit.
0 = No effect on TXD output
1 = Forces TXD output to 0 (space)
Bit Reset
Value
0b
0b
Bit Access
RW
RW
Intel^® EP80579 Integrated Processor Product Line Datasheet
1182
August 2009
Order Number: 320066-003US