EP80579 Datasheet, PDF (1218/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 34-5. Offset 4h: PCICMD: Device Command Register (Sheet 2 of 2)
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:4:0
Offset Start: 4h
Offset End: 5h
Size: 16 bit
Default: 0h
Power Well: Core
Bit Range Bit Acronym
Bit Description
04
MWE
Memory Write and Invalidate
03
SS
Special Cycle
02
BM
Bus Master Capable
01
MEM
Memory Space Enable
00
IO
I/O Space Enable
Sticky
Bit Reset
Value
0h
0h
0h
0h
0h
Bit Access
RO
RO
RW
RW
RW
34.2.2.4 Offset 6h: PCISTS – Device Status Register
Table 34-6. Offset 6h: PCISTS: PCI Device Status Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:4:0
Offset Start: 6h
Offset End: 7h
Size: 16 bit
Default: 10h
Power Well: Core
Bit Range Bit Acronym
Bit Description
15
14
13
12
11
10 : 09
08
07
06
05
04
03
02 : 00
DPE
SSE
RMA
RTA
STA
DST
MDPE
FB2B
RV
MC66
CL
IS
RV
Detected Parity Error
Signaled System Error
Received Master Abort
Received Target Abort
Signaled Target Abort
DEVSEL Timing
Master Data Parity Error
Fast Back-to-Back Capable
Reserved
66 MHz Capable
Capabilities List
Interrupt Status
Reserved
Sticky
Bit Reset
Value
0h
0h
0h
0h
0h
00b
0h
0h
0h
0h
1
0h
0h
Bit Access
RO
RO
RO
RO
RO
RO
RO
RO
RV
RO
RO
RO
RV
Intel^® EP80579 Integrated Processor Product Line Datasheet
1218
August 2009
Order Number: 320066-003US