EP80579 Datasheet, PDF (760/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
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19.3.5
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19.3.6
19.3.7
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19.3.8
19.3.9
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19.3.10
If the cycle is not claimed by any peripheral (and subsequently aborted), a value of all
1s (FFh) is returned to the processor. This is to maintain compatibility with legacy
memory cycles where pull-up resistors would keep the bus high if no device responds.
I/O Cycle Notes
For I/O cycles targeting registers specified in the decode ranges, CMI performs I/O
cycles as defined in the LPC Specification. These are 8-bit transfers. If the processor
attempts a 16-bit or 32-bit transfer, CMI breaks the cycle up into multiple 8-bit
transfers to consecutive I/O addresses until the request is satisfied.
If the cycle is not claimed by any peripheral (and subsequently aborted), CMI returns a
value of all 1s (FFh) to the processor. This is to maintain compatibility with legacy I/O
cycles where pull-up resistors would keep the bus high if no device responds.
DMA Cycle Notes
Only 8-bit and 16-bit DMA transfers are supported. Peripherals must not attempt 32-bit
transfers.
Bus Master Cycle Notes
CMI supports Bus Master cycles and requests (using LDRQ#) as defined in the LPC
Specification. CMI has two LDRQ# inputs, and thus supports two separate bus master
devices. It uses the associated START fields for Bus Master 0 (0010b) or Bus Master 1
(0011b).
CMI does not support LPC Bus Masters performing I/O cycles. LPC Bus Masters must
only perform memory read or memory write cycles and must only target main memory.
FWH Cycle Notes
A FWH device is not allowed to assert an Error SYNC. If the LPC controller receives any
SYNC returned from the device other than short wait (0101), long wait (0110), or
ready more (0000) when running a FWH cycle, indeterminate results will occur.
LPC PD# Protocol
The LPCPD# pin must follow the same timings as for SUS_STAT#.Upon driving
SUS_STAT# low, LPC peripherals will drive LDRQ# low or tri-state it. The LPC Controller
must shut the LDRQ# input buffers. After driving SUS_STAT# active, the LPC Controller
drives LFRAME# low, and tri-states (or drive low) LAD[3:0].
The LPC Controller does not follow one part of the LPC Specification that says
“LRESET# is always asserted after LPCPD#”. LRESET# is not always asserted after
LPCPD#. The Low Pin Count Interface Specification, Revision 1.1 defines the LPCPD#
protocol where there is at least 30 µs from LPCPD# assertion to LRST# assertion. This
specification explicitly states that this protocol only applies to entry/exit of low power
states which does not include asynchronous reset events. CMI asserts both SUS_STAT#
(connects to LPCPD#) and PLTRST# (connects to LRST#) at the same time when the
core logic is reset (via CF9h, PWROK, or SYS_RESET#, etc.). This is not inconsistent
with the LPC LPCPD# protocol.
Cycle Posting Policies
Three main policies are assumed.
Intel^® EP80579 Integrated Processor Product Line Datasheet
760
August 2009
Order Number: 320066-003US