EP80579 Datasheet, PDF (1034/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
26.11.3
26.11.4
1. Configure Flag = 0 and a Classic-only Device is connected
In this case, the classic Host Controller is the owner of the port both before and
after the connect occurs; the EHC (except for the port-routing logic) never sees the
connect occur. The UHCI driver handles the connection and initialization process.
2. Configure Flag = 0 and an Enhanced-capable Device is connected
In this case, the classic Host Controller is the owner of the port both before and
after the connect occurs; the EHC (except for the port-routing logic) never sees the
connect occur. The UHCI driver handles the connection and initialization process.
Since the classic Host Controller does not perform the high-speed chirp handshake,
the device operates in compatible mode.
3. Configure Flag = 1 and a Classic-only Device is connected
In this case, the enhanced Host Controller is the owner of the port before the
connect occurs. The EHCI driver checks the Line Status bits to determine if a low-
speed device is connected. If so, then the Port Owner bit is written to a 1 and the
UHCI driver handles the reset sequence. If a low-speed device is not detected
through the Line Status bits, the EHCI driver handles the connection and performs
the port reset. After the reset process completes, the EHC hardware has cleared
(not set) the Port Enable bit in the EHC’s PORTSC register. The EHCI driver then
writes a 1 to the Port Owner bit in the same register, causing the classic Host
Controller to see a connect event and the EHC to see an “electrical” disconnect
event. The UHCI driver and hardware handle the connection and initialization
process from that point on. The EHCI driver and hardware handle the perceived
disconnect.
4. Configure Flag = 1 and an Enhanced-capable Device is connected
In this case, the enhanced Host Controller is the owner of the port before, and
remains the owner after, the connect occurs. The EHCI driver handles the
connection and performs the port reset. After the reset process completes, the EHC
hardware has set the Port Enable bit in the EHC’s PORTSC register. The port is
functional at this point. The classic Host Controller continues to see an unconnected
port.
Device Disconnects
The EHCI Specification, Rev. 1.0 describes the details of handling Device Connects.
There are three general scenarios that are summarized below.
1. Configure Flag = 0 and the device is disconnected
In this case, the classic Host Controller is the owner of the port both before and
after the disconnect occurs; the EHC (except for the port-routing logic) never sees
a device attached. The UHCI driver handles disconnection process.
2. Configure Flag = 1 and a Classic Device is disconnected
In this case, the classic Host Controller is the owner of the port before the
disconnect occurs. The disconnect is reported by the classic Host Controller and
serviced by the associated UHCI driver. The port-routing logic in the EHC cluster
forces the Port Owner bit to 0, indicating that the EHC owns the unconnected port.
3. Configure Flag = 1 and an Enhanced Device is disconnected
In this case, the enhanced Host Controller is the owner of the port before, and
remains the owner after, the disconnect occurs. The EHCI hardware and driver
handle the disconnection process. The classic Host Controller never sees a device
attached.
Effect of Resets on Port-Routing Logic
As mentioned above, the Port Routing logic is implemented in the Suspend power well
so that reenumeration and remapping of the USB ports is not required following
entering and exiting a system sleep state in which the core power is turned off.
Intel^® EP80579 Integrated Processor Product Line Datasheet
1034
August 2009
Order Number: 320066-003US