EP80579 Datasheet, PDF (1173/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
• Fully programmable serial-interface characteristics:
• 5, 6, 7 or 8-bit characters.
• Even, odd, or no parity detection.
• 1, 1-1/2, or 2 stop bit generation.
• Baud rate generation (up to 115 kbps).
• False start bit detection.
• 16-byte Receive FIFO.
• Complete status reporting capability.
• Line break generation and detection.
• Internal diagnostic capabilities include:
— Loopback controls for communications link fault isolation.
— Break, parity, overrun, and framing error simulation.
— Fully prioritized interrupt system controls.
33.5.2 UART Operational Description
The format of a UART data frame is shown in Figure 33-1.
Figure 33-1. Example UART Data Frame
Each data frame is between seven bits and 12 bits long depending on the size of data
programmed, if parity is enabled and if two stop bits is selected. The frame begins with
a start bit that is represented by a high to low transition. Next, 5 to 8 bits of data are
transmitted, beginning with the least significant bit. An optional parity bit follows,
which is set if even parity is enabled and an odd number of ones exist within the data
byte, or if odd parity is enabled and the data byte contains an even number of ones.
The data frame ends with one, one and a half or two stop bits as programmed by the
user, which is represented by one or two successive bit periods of a logic one.
The unit is disabled upon reset, the user needs to enable the unit by setting bit six of
Interrupt Enable Register. When the unit is enabled, the receiver starts looking for the
start bit of a frame; the transmitter starts transmitting data to the transmit data pin if
there is data available in the transmit FIFO. Transmit data can be written to the FIFO
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
1173