EP80579 Datasheet, PDF (1758/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
48.4.3.10 IICH Miscellaneous Signals
Table 48-20. IICH Miscellaneous Signals
Signal Name
CLK14
IO Type
LVTTL,3.3V
Direction
Ball
Count
I
1
External
Pull-Up/
Down
[Ohms]
BSC/
XOR
Signal Description Normal/Alternate Mode
BSC
Timer Oscillator Clock: Used for 8254 timers and
HPET (High Precision Event Timer). Runs at
14.31818 MHz. This clock stops (and should be
low) during S3 and S5 state. CLK14 must be
accurate to within 500ppm over 100usecs (and
longer periods) in order to meet HPET accuracy
requirements.
PE_HPINTR#
LVTTL,3.3V I
1
BSEL
LVTTL,3.3V O
1
V_SEL
LVTTL,3.3V I/OD
1
WDT_TOUT#
LVTTL,3.3V O
1
TOTAL
5
10K to
100K Up
10K Up
BSC
BSC
BSC
BSC
IMCH PCI Express Hot-plug Controller Interrupt:
Input pin to hot-plug controller on PCI Express
bus. Not 5V tolerant.
Note: Because PCI Express Hot Plug is not
supported in the EP80579, this pin must be
pulled up to 3.3V through a 10K to 100K pull-up
resistor.
IA FSB Frequency Select: The CPU Select (BSEL)
encodings are used at power-on to specify the
frequency mode of the FSB PLL circuitry.
The EP80579 interprets BSEL as follows:
0 = 400MHz FSB
1 = 533MHz FSB
BSEL is driven by the on-die CPU based on its
configuration.
IA Voltage Select: The voltage select encodings
are used in conjunction with BSEL at power-on
to specify the operating voltage of the IA CPU.
This signal is a 3.3V OD output with an external
pullup.
The EP80579 interprets V_SEL as follows when
BSEL is 0 (400MHz FSB):
0 = 1.00V IA core voltage VCCVC
1 = Reserved
and as follows when BSEL is 1 (533MHz FSB):
0 = 1.30V IA core voltage VCCVC
1 = 1.30V IA core voltage VCCVC
The voltage supply for these pins must be valid
before the Voltage Regulator can supply VCCVC
to the processor. The V_SEL pin is needed to
support the processor voltage specification
variations defined above. The VR must supply
the voltage that is requested by the pins.
Watchdog Timer Output Signal: The signal is
driven low when the main 35-bit down counter
reaches zero during the second stage. The
WDT_TOUT_CNF bit in the WDT Lock register
determines if the output is to change from the
previous state if another time out occurs, or
WDT_TOUT_N is driven low until the system is
reset or power is cycled.
Intel^® EP80579 Integrated Processor Product Line Datasheet
1758
August 2009
Order Number: 320066-003US