EP80579 Datasheet, PDF (1402/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
The Virtual LAN ID field indexes a 4096 bit vector. If the indexed bit in the vector is
one; there is a Virtual LAN match. Software may set the entire bit vector to ones if the
node does not implement 802.1q filtering. The register description of the VLAN Filter
Table Array is described in detail in “VFTA[0-127] – 128 VLAN Filter Table Array
Registers” on page 1490.
In summary, the 4096 bit vector is comprised of 128, 32-bit registers. Matching to this
bit vector follows the same algorithm as indicated in section 0 for Multicast Address
filtering. The VLAN Identifier (VID) field consists of 12 bits. The upper 7 bits of this field
are decoded to determine the 32-bit register in the VLAN Filter Table Array to address
and the lower 5 bits determine which of the 32 bits in the register to evaluate for
matching.
Two other bits RCTL.CFIEN and RCTL.CFI (refer to “RCTL – Receive Control Register” on
page 1474), are also used in conjunction with 802.1q VLAN filtering operations.
RCTL.CFIEN enables the comparison of the value of the RCTL.CFI bit to the 802.1q
packet data as an acceptance criteria for the packet.
Note:
The VFE bit does not effect whether the VLAN tag is stripped. It only effects whether
the VLAN packet passes the receive filter.
The following table lists reception actions per control bit settings.
Table 37-5. Packet Reception Decision Table
Is
packet
802.1q?
No
Yes
CTRL.
VME
X
0
Yes
0
Yes
1
Yes
1
RCTL.
VFE
Action
X
Normal packet reception
0
Receive a VLAN packet if it passes the standard filters (only). Leave the
packet as received in the data buffer. VP bit in receive descriptor is clear.
Receive a VLAN packet if it passes the standard filters and the VLAN filter
1
table. Leave the packet as received in the data buffer (e.g. the VLAN tag
would not be stripped). VP bit in receive descriptor is clear.
Receive a VLAN packet if it passes the standard filters (only). Strip off the
0
VLAN information (four bytes) from the incoming packet and store in the
descriptor. Set VP bit in receive descriptor.
Receive a VLAN packet if it passes the standard filters and the VLAN filter
1
table. Strip off the VLAN information (four bytes) from the incoming packet
and store in the descriptor. Set VP bit in receive descriptor.
Note:
A packet is defined as a VLAN/802.1q packet if its type field matches the VET.
37.5.10
Wake on LAN
Two types of wakeup mechanisms are supported:
• Advanced Power Management (APM) Wakeup
• ACPI Power Management Wakeup
When so configured, if a wake-up packet is received, the GBE_PME_WAKE signal will be
asserted. The GBE_PME_WAKE signal of all three GbE MACs are wired-or together and
brought to the external pin GBE_PME_WAKE. The user must externally connect this pin
to the PME_N input pin.
37.5.10.1 Advanced Power Management Wakeup
“Advanced Power Management Wakeup”, or “APM Wakeup”, was previously known as
“Wake on LAN”. It is an feature that has existed in ethernet NICs for several
generations. The basic premise is to receive a broadcast or unicast packet with an
Intel^® EP80579 Integrated Processor Product Line Datasheet
1402
August 2009
Order Number: 320066-003US