EP80579 Datasheet, PDF (269/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Figure 10-2. DOS Legacy Region
10 0000h
Standard PCI/ISA
Video Memory
(SMM Memory)
0C0000h
0B8000h
0B0000h
0A0000h
Upper, Lower,
Expansion Card BIOS
and Buffer Area
VGAB
Monchrome Display
Adapter Space
VGAA
1MB
768 KB
736 KB
704 KB
640 KB
Key
Controlled
by
PAM[6:0].
Controlled
by
VGA Enable and
MDA enable.
= Optionally DRAM
= DRAM
If the configuration bit EXSMRC.MDAP (see Section 16.1.1.25, “Offset 9Dh: EXSMRC -
Extended System Management RAM Control Register”) is set, then accesses that fall
within the MDA range are sent to NSI without regard for the VGAEN bits. Legacy
support requires the ability to have a second graphics controller (monochrome display
adapter) in the system. In a CMI system with PCI graphics installed via a PCIe to PCI
bridge like PXH, accesses in the standard VGA range may be forwarded to any of the
logical PCI Express ports (depending on configuration bits). Since the monochrome
adapter may be on the NSI (or logical ISA) bus, the IMCH must decode cycles in the
MDA range and forward them to NSI. This capability is controlled via the MDAP
configuration bit. In addition to the memory range B0000h to B7FFFh, the IMCH
decodes I/O cycles at 3B4h, 3B5h, 3B8h, 3B9h, 3BAh and 3BFh and forwards them to
NSI.
An optimization allows the system to reclaim the memory displaced by these regions. If
SMM memory space is enabled by EXSMRC.G_SMRAME and either the SMRAM.D_OPEN
bit (see Section 16.1.1.25, “Offset 9Dh: EXSMRC - Extended System Management RAM
Control Register” and Section 16.1.1.26, “Offset 9Eh: SMRAM - System Management
RAM Control Register”) is set or the processor bus receives an SMM-encoded request
for code (not data), then the transaction is steered to system memory rather than NSI.
Under these conditions, both the VGAEN bits and the MDAP bit are overridden.
If any VGAEN bit is set, then all ISAEN bits (see Section 16.4.1.26, “Offset 3Eh: BCTRL
- Bridge Control Register”) must be set. The PCI Specification defines VGAEN to be 10-
bit decode. Therefore the other peer bridges must also be 10-bit decodes (ISAEN), so
that two or more devices don't claim same access. (Bridge C doesn't know bridge B has
its VGAEN bit set.)
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
269