EP80579 Datasheet, PDF (79/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Contents
35-140 Offset E6h: SBC: Signal Target Byte Count Register ...........................................1314
35-141 Offset E7h: STYP: Signal Target Capability Type Register ....................................1315
35-142 Offset E8h: SMIA: Signal Target IA Mask Register ..............................................1315
35-143 Offset ECh: SINT: Signal Target Raw Interrupt Register .......................................1316
35-144 Offset F0h: MCID: Message Signalled Interrupt Capability ID Register ..................1316
35-145 Offset F1h: MCP: Message Signalled Interrupt Next Capability Pointer Register ......1317
35-146 Offset F2h: MCTL: Message Signalled Interrupt Control Register ..........................1317
35-147 Offset F4h: MADR: Message Signalled Interrupt Address Register ........................1318
35-148 Offset F8h: MDATA: Message Signalled Interrupt Data Register ...........................1318
35-149 Bus M, Device 8, Function 0: Summary of Local Expansion Bus PCI
Configuration Registers ....................................................................................1319
35-150 Offset 00h: VID: Vendor Identification Register .................................................1320
35-151 Offset 02h: DID: Device Identification Register .................................................1320
35-152 Offset 04h: PCICMD: Device Command Register ................................................1321
35-153 Offset 06h: PCISTS: PCI Device Status Register ................................................1321
35-154 Offset 08h: RID: Revision ID Register ..............................................................1322
35-155 Offset 09h: CC: Class Code Register ................................................................1323
35-156 Offset 0Eh: HDR: Header Type Register ............................................................1323
35-157 Offset 10h: CSRBAR: Control and Status Registers Base Address Register .............1324
35-158 Offset 14h: MMBAR: Expansion Bus Base Address Register .................................1324
35-159 MMBAR ADDR Field Behavior ............................................................................1325
35-160 Offset 2Ch: SVID: Subsystem Vendor ID Register ..............................................1325
35-161 Offset 2Eh: SID: Subsystem ID Register ...........................................................1326
35-162 Offset 34h: CP: Capabilities Pointer Register .....................................................1326
35-163 Offset 3Ch: IRQL: Interrupt Line Register .........................................................1326
35-164 Offset 3Dh: IRQP: Interrupt Pin Register ..........................................................1327
35-165 Offset 40h: LEBCTL: LEB Control Register ..........................................................1327
35-166 Offset DCh: PCID: Power Management Capability ID Register ..............................1327
35-167 Offset DDh: PCP: Power Management Next Capability Pointer Register .................1328
35-168 Offset DEh: PMCAP: Power Management Capability Register ................................1328
35-169 Offset E0h: PMCS: Power Management Control and Status Register .....................1329
35-170 Offset E4h: SCID: Signal Target Capability ID Register .......................................1329
35-171 Offset E5h: SCP: Signal Target Next Capability Pointer Register ...........................1330
35-172 Offset E6h: SBC: Signal Target Byte Count Register ...........................................1330
35-173 Offset E7h: STYP: Signal Target Capability Type Register ....................................1330
35-174 Offset E8h: SMIA: Signal Target IA Mask Register ..............................................1331
35-175 Offset ECh: SINT: Signal Target Raw Interrupt Register .......................................1331
35-176 Offset F0h: MCID: Message Signalled Interrupt Capability ID Register ..................1332
35-177 Offset F1h: MCP: Message Signalled Interrupt Next Capability Pointer Register ......1332
35-178 Offset F2h: MCTL: Message Signalled Interrupt Control Register ..........................1333
35-179 Offset F4h: MADR: Message Signalled Interrupt Address Register ........................1333
35-180 Offset F8h: MDATA: Message Signalled Interrupt Data Register ...........................1334
37-1 Supported Receive Checksum Capabilities ........................................................1363
37-2 VLAN Tag Insertion Decision Table when VLAN Mode Enabled (CTRL.VME=1) ..........1368
37-3 VLAN Tag Insertion Decision Table.....................................................................1374
37-4 Untagged 802.3 Packet vs 802.1q VLAN tagged Packet ........................................1400
37-5 Packet Reception Decision Table........................................................................1402
37-6 EEPROM Address Map ......................................................................................1413
37-7 Initialization Control Word 1 .............................................................................1415
37-8 Initialization Control Word 2 .............................................................................1416
37-9 Initialization Control Word 3 .............................................................................1416
37-10 Management Control Word ...............................................................................1416
37-11 IPv4 Address ..................................................................................................1417
37-12 IPv6 Address ..................................................................................................1417
37-13 Memory protection ..........................................................................................1419
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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