EP80579 Datasheet, PDF (208/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 7-20. Bus 0, Device 29, Function 7: Summary of USB (2.0) Controller Configuration
Registers Mapped Through MBAR Memory BAR
Offset Start Offset End
Register ID - Description
Default
Value
00h
02h
04h
08h
20h
24h
28h
2Ch
30h
34h
38h
60h
64h
68h
A0h
A4h
A8h
B0h
00h
03h
07h
0Bh
23h
27h
2Bh
2Fh
33h
37h
3Bh
63h
67h
6Bh
A3h
A4h
AFh
B0h
“Offset 00h: CAPLENGTH - Capability Length Register” on page 1002
20h
“Offset 02h: HCIVERSION - Host Controller Interface Version Number Register” on
page 1003
0100h
“Offset 04h: HCSPARAMS - Host Controller Structural Parameters Register” on
page 1003
01001202h
“Offset 08h: HCCPARAMS - Host Controller Capability Parameters Register” on
page 1004
00006871h
“Offset 20h: USB2CMD - USB 2.0 Command Register” on page 1007
00080000h
“Offset 24h: USB2STS - USB 2.0 Status Register” on page 1009
00001000h
“Offset 28h: USB2INTR - USB 2.0 Interrupt Enable Register” on page 1012
00000000h
“Offset 2Ch: FRINDEX - Frame Index Register” on page 1013
00000000h
“Offset 30h: CTRLDSSEGMENT - Control Data Structure Segment Register” on
page 1014
00000000h
“Offset 34h: PERIODICLISTBASE - Periodic Frame List Base Address Register” on
page 1014
00000XXXh
“Offset 38h: ASYNCLISTADDR - Current Asynchronous List Address Register” on
page 1015
00000000h
“Offset 60h: CONFIGFLAG - Configure Flag Register” on page 1015
00000000h
“Offset 64h: PORTSC - Port N Status and Control Register” on page 1016
00003000h
“Offset 64h: PORTSC - Port N Status and Control Register” on page 1016
00003000h
“Offset A0h: CNTL_STS - Control/Status Register” on page 1037
00000000h
“Offset A4h: USBPID - USB PIDs Register” on page 1039
00000000h
“Offset A8h: DATABUF - Data Buffer Bytes 7:0” on page 1039
00000000000
00000h
“Offset B0h: CONFIG - Configuration Register” on page 1040
00007F01h
Intel^® EP80579 Integrated Processor Product Line Datasheet
208
August 2009
Order Number: 320066-003US