EP80579 Datasheet, PDF (782/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
20.5.5
20.5.6
Note:
Note:
Verify Mode
Verify mode is supported on the LPC interface. A verify transfer to the peripheral is
similar to a DMA write, where the peripheral is transferring data to main memory. The
indication from the host is the same as a DMA write, so the peripheral is driving data
onto the LPC interface. However, the host does not transfer this data into main
memory.
DMA Request Deassertion
An end of transfer is communicated to the IICH through a special SYNC field
transmitted by the peripheral. If a DMA transfer is several bytes, such as a transfer
from a demand mode device, the IICH needs to know when to deassert the DMA
request based on the data currently being transferred.
The DMA agent uses a SYNC encoding on each byte of data being transferred, which
indicates to the IICH whether this is the last byte of transfer or if more bytes are
requested. To indicate the last byte of transfer, the peripheral uses a SYNC value of
‘0000b’ (ready with no error), or ‘1010b’ (ready with error). These encodings tell the
IICH that this is the last piece of data transferred on a DMA read (IICH to peripheral),
or the byte which follows is the last piece of data transferred on a DMA write
(peripheral to IICH).
When the IICH sees one of these two encodings, it ends the DMA transfer after this
byte and deasserts the DMA request to the 8237. Therefore, if the IICH indicated a 16
bit transfer, the peripheral can end the transfer after one byte by indicating a SYNC
value of ‘0000b’ or ‘1010b’. The IICH does not attempt to transfer the second byte, and
deasserts the DMA request internally. This allows the peripheral, therefore, to
terminate a DMA burst.
If the peripheral indicates a ‘0000b’ or ‘1010b’ SYNC pattern on the last byte of the
indicated size, then the IICH only deasserts the DMA request to the 8237 since it does
not need to end the transfer.
If the peripheral wishes to keep the DMA request active, then it uses a SYNC value of
‘1001b’ (ready plus more data). This tells the 8237 that more data bytes are requested
after the current byte has been transferred, so the IICH keeps the DMA request active
to the 8237. Therefore, on an 8 bit transfer size, if the peripheral indicates a SYNC
value of ‘1001b’, the data is transferred and the DMA request remains active to the
8237. At a later time, the IICH starts with another START ⇒ CYCTYPE ⇒ CHANNEL ⇒
SIZE etc. combination to initiate another transfer to the peripheral.
The peripheral must not assume that the next START indication from the IICH is
another grant to the peripheral if it had indicated a SYNC value of ‘1001b’. On a single
mode DMA device, the 8237 rearbitrates after every transfer. Only demand mode DMA
devices can be guaranteed that they receive the next START indication from the IICH.
Indicating a ‘0000b’ or ‘1010b’ encoding on the SYNC field of an odd byte of a 16 bit
channel (first byte of a 16 bit transfer) is an error condition.
The host stops the transfer on the LPC bus as indicated, fill the upper byte with random
data on DMA writes (peripheral to memory), and indicate to the 8237 that the DMA
transfer occurred, incrementing the 8237s address and decrementing its byte count.
Intel^® EP80579 Integrated Processor Product Line Datasheet
782
August 2009
Order Number: 320066-003US