EP80579 Datasheet, PDF (55/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Contents
49-30
49-31
49-32
49-33
49-34
49-35
49-36
49-37
49-38
49-39
49-40
49-41
49-42
49-43
49-44
49-45
49-46
49-47
49-48
49-49
49-50
LPC Float Delay Diagram ..................................................................................1874
IICH Interrupt Signal Timing Diagram ................................................................1876
IICH Clock (CLK14) Timing Diagram ..................................................................1877
RTC Clock Output (SUSCLK) Timing Diagram ......................................................1878
GbE RGMII Mode Signal Connection Block Diagram ..............................................1883
RGMII 125 MHz Reference Clock Timing Diagram ................................................1884
GbE Transmit Waveform — RGMII Mode.............................................................1885
GbE Receive Waveform — RGMII Mode ..............................................................1886
GbE RMII Mode Signal Connection Block Diagram — External Clock Source .............1887
GbE RMII Transmit and Receive Waveforms — RMII Mode ....................................1887
MDIO Output Timing Diagram (EP80579 is Sourcing MDIO) ..................................1888
MDIO Input Timing Diagram (PHY is Sourcing MDIO) ...........................................1888
EEPROM Interface Timing Diagram ....................................................................1889
TDM, Serial Timings.........................................................................................1894
Local Expansion Bus Synchronous Timing ...........................................................1896
SSP Signal Connection Block Diagram - Multi-Drop Connections ............................1899
SSP Interface Timing Diagram ..........................................................................1900
CRU Differential Clock Waveform.......................................................................1903
CRU Differential Clock Cross-Point Specification...................................................1904
JTAG Output Timing Measurement Waveforms ....................................................1908
JTAG Input Timing Measurement Waveforms ......................................................1909
Tables
1-1
1-2
1-3
1-4
2-1
2-2
2-3
2-4
2-5
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10
3-11
3-12
4-1
5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-8
Referenced Documents ...................................................................................... 94
Related Websites ............................................................................................... 95
Acronym Table................................................................................................... 95
Glossary Table .................................................................................................. 98
EP80579 External Interface Summary ................................................................ 106
IA-32 core / FSB Frequency Ratios (depends on SKU and configuration) .................. 107
Memory Controller Frequencies .......................................................................... 107
Summary of Communication .............................................................................. 107
DMA and Peer-to-Peer Data Transfer Options ....................................................... 109
Main Memory DRAM Organization ..................................................................... 112
Basic CMI Platform Address Space Requirements for IMCH and IICH Devices............ 115
Memory Regions .............................................................................................. 116
Supported Operations by Memory Type ............................................................... 117
Supported Operations by Memory Type ............................................................... 118
Device Exposure from an IA-attached Memory Map Perspective .............................. 119
Address Space Sizes of AIOC-attached Devices .................................................... 119
Expansion Bus Byte Ordering for Inbound Transactions using LEBCTL register .......... 119
IMCH and IICH PCI Device Summary .................................................................. 122
AIOC PCI Device Summary ................................................................................ 123
PCI Configuration Header Support for Type 0 Headers in AIOC Devices ................... 125
PCI Configuration Header Support for Type 1 Headers in AIOC Devices ................... 127
Supported Inter-Agent Signaling ........................................................................ 134
Summary of IMCH Global Error Conditions ........................................................... 142
Summary of IMCH Buffer Unit Error Conditions..................................................... 143
Summary of IMCH Buffer Unit Error Reporting Capabilities ..................................... 143
Summary of IMCH FSB Error Conditions .............................................................. 144
Summary of IMCH FSB Error Reporting Capabilities .............................................. 144
Summary of IMCH NSI Error Conditions .............................................................. 145
Summary of IMCH NSI Error Reporting Capabilities............................................... 146
Summary of IMCH EDMA Error Conditions ........................................................... 146
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
55