EP80579 Datasheet, PDF (881/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
23.5.5.3.2 Device D1, D3 States
These states are entered after some period of time when software has determined that
no commands will be sent to this device for some time. The mechanism for putting a
device in these states does not involve any work on the host controller, other then
sending commands over the interface to the device. The command most likely to be
used in ATA/ATAPI is the “STANDBY IMMEDIATE” command.
23.5.5.3.3 Host Controller D3 state
After the interface and device have been put into a low power state, the host controller
may be put into a low power state. This is performed via the PCI power management
registers in configuration space.
There are two very important aspects to note when using PCI power management.
1. When the power state is D3, only accesses to configuration space are allowed. Any
attempt to access the memory or I/O spaces must result in master abort.
2. When the power state is D3, no interrupts may be generated, even if they are
enabled. If an interrupt status bit is pending when the controller transitions to D0,
an interrupt may be generated.
When the controller is put into D3, it is assumed that software has properly shut down
the device and disabled the ports. Therefore, there is no need to sustain any values on
the port wires. The interface will be treated as if no device is present on the cable, and
power will be minimized.
When returning from a D3 state, an internal reset will not be performed. When in
legacy mode of operation, the SATA controller does not generate PME#. This includes
attach events (since the port must be disabled), or interlock switch events (via the
SATAGP pins).
23.5.5.4
SMI Trapping (APM)
The ATC register in configuration space contains control for generating SMI# on
accesses to the IDE I/O spaces. These bits map to the legacy ranges only (1f0h-1f7h,
3f4h-3f6h, 170h-177h, and 374h-376h). Trapping will not occur on the native IDE
ranges defined by PCMDBA, PCTLBA, SCMDBA, SCTLBA, or LBAR. If the SATA controller
is in legacy mode and is using these addresses, accesses to one of these ranges with
the appropriate bit set will cause the cycle to not be forwarded to the SATA controller,
and for SMI# to be generated.
SMI trapping is specifically supported in the following configurations:
• SATA controller in legacy addressing mode (non-combined).
Additionally, an ATS register bit will get set on an access to these ranges if the
corresponding bit in the ATC register is set.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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