EP80579 Datasheet, PDF (360/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Note:
14.1.2
14.1.2.1
14.1.2.2
14.1.2.3
this scheme; meaning that the total number of asserted bits including the parity bits is
an even number of bits. This parity protection scheme applies to different interfaces on
the chip hence the name: “Chip Two Bit Parity” or CTB parity.
Due to EDMA byte realignment and parity manipulation, a single CTB parity bit error
observed by the EDMA unit may poison either 2 or 4 DWords depending on the
resultant alignment. Refer to the EDMA chapter for more details.
DRAM Data Integrity
Periodic Memory Scrubbing
When enabled a special DRAM memory scrubbing unit will walk through all DRAM, on a
periodic basis, doing reads. Correctable errors found by the read are corrected and
then the good data written back to DRAM. A write is only performed when a single bit
error has been detected and is correctable, except when an incoming write to the same
memory address is detected. In this case the scrub write is dropped and the scrub
counter is advanced since this location is already being written. These transactions are
treated as non-coherent, since these addresses are not placed on the FSB.
The scrub unit starts at an address than can be programmed and counts to 0. The
scrub rate is also programmable so using this method, a 4 GB system can be
completely scrubbed in less than a day. The cumulative effect of these scrub writes do
not cause any noticeable degradation to memory bandwidth, although they will cause a
greater latency for that one very infrequent read that is delayed due to the scrub write
cycle.
DRAM Hardware Initialization
Hardware will be used to initialize main memory under the direction of BIOS. Once
BIOS has programmed the IMCH with the DIMM profile, and has configured and
calibrated the IMCH and populated DIMMs, it can utilize the MBIST CSRs to initialize
and/or test populated memory. The initialization of MBISTCSR will traverse the target
range of memory addresses as rapidly as possible, providing an order of magnitude
performance improvement over IA-32 core-generated initialization or test.
The MBIST engine can be configured to choose values other than zero. The eight fixed
hex data values selectable are alternating pairs of 0/F, A/5, 3/C, or 6/9. Alternate
modes are provided in which LFSR random data may be used, or software explicitly
specifies the full pattern of bits to be written in a collection of MBIST DATA registers
with or without a shift after every write. In all cases of pattern based initialization and
test, the MBIST function does NOT calculate ECC on the fixed pattern or programmed
value to be written across the target address range. Rather, the fixed pattern is
extended to cover the data devices as well as the ECC devices in the target DIMM, and
a strict bit-wise comparison is utilized to determine whether read-back verification
passes or fails.
Once all desired testing has been completed, WHQL requirements dictate that memory
be completely initialized to “0” prior to transferring control to the operating system. To
accomplish this, BIOS must clear all the MBISTDATA registers and utilize the explicit
pattern mode of MBIST. It is possible to initialize memory a rank at a time, or en-
masse, at the discretion of BIOS.
Uncorrectable Retries
The memory controller will not support uncorrectable retries.
Intel^® EP80579 Integrated Processor Product Line Datasheet
360
August 2009
Order Number: 320066-003US