EP80579 Datasheet, PDF (1463/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 37-42. ICR1: Interrupt 1Cause Read Register (Sheet 2 of 3)
Description:
View: PCI 1
BAR: CSRBAR
Bus:Device:Function: M:0:0
Offset Start: 08C0h
Offset End: 08C3h
View: PCI 2
BAR: CSRBAR
Bus:Device:Function: M:1:0
Offset Start: 08C0h
Offset End: 08C3h
View: PCI 3
BAR: CSRBAR
Bus:Device:Function: M:2:0
Offset Start: 08C0h
Offset End: 08C3h
Size: 32 bits
Default: 00000000h
GbE0: Aux
Power Well: Gbe1/2:
Core
Bit Range
21
20
19 : 17
16
15
14 : 8
07
06
05
04
03
02
Bit Acronym
Bit Description
Sticky
ERR_TXDS
ERR_RXDS
RSVD
SRPD
TXD_LOW
Rsvd
RXT0
RXO
Rsvd
RXDMT0
Rsvd
RSVD
DMA Transmit Descriptor 2-bit ECC Error. The DMA
Transmit Descriptor Buffer uses a single-bit correct/multi-
bit detect ECC parity algorithm to protect the SRAM it uses
for a data buffer. This bit indicates that a multi-bit error
has occurred on a read from that data buffer. No indication
of a single-bit error correction will be given by hardware.
Note: If this interrupt asserts, further GbE DMA Reads
and Writes are blocked until software issues a soft
reset to the GbE by writing the Device Control
Register (CTRL.RST).
DMA Receive Descriptor 2-bit ECC Error. The DMA Receive
Descriptor Buffer uses a single-bit correct/multi-bit detect
ECC parity algorithm to protect the SRAM it uses for a data
buffer. This bit indicates that a multi-bit error has occurred
on a read from that data buffer. No indication of a single-
bit error correction will be given by hardware.
Note: If this interrupt asserts, further GbE DMA Reads
and Writes are blocked until software issues a soft
reset to the GbE by writing the Device Control
Register (CTRL.RST).
Reserved
Small Receive Packet Detected.
Indicates that a packet of size RSRPD.SIZE register has
been detected and transferred to host memory. The
interrupt is only asserted if RSRPD.SIZE register has a
non-zero value
Transmit Descriptor Low Threshold hit. Indicates that the
descriptor ring has reached the threshold specified in
“TXDCTL – Transmit Descriptor Control Register” on
page 1500.
Reserved
Receiver Timer Interrupt. Set when the timers expire,
see “Receive Interrupts” on page 1360 for details.
Receiver Overrun. Set on receive data FIFO overrun.
Could be caused either because there are no available
buffers or because Internal Bus receive bandwidth is
inadequate.
Reserved
Receive Descriptor Minimum Threshold Hit. Indicates
that the minimum number of receive descriptors are
available and software should load more receive
descriptors.
Reserved
Reserved
Bit Reset
Value
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
Bit Access
RCWC
RCWC
RV
RCWC
RCWC
RV
RCWC
RCWC
RV
RCWC
RCWC
RV
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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