EP80579 Datasheet, PDF (942/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
25.1.1
25.1.1.1
Register Details
ID - Identifiers Register
Table 25-2. ID - Identifiers Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:29:0
Offset Start: 00h
Offset End: 03h
Size: 32 bit
Default: 50338086h
Power Well: Core
Bit Range Bit Acronym
Bit Description
31 : 16
Device ID: This 16-bit field is defined as follows:
DID
Function 0 5033h
Sticky
Bit Reset
Value
Bit Access
5033h
RO
15 : 00
VID
Vendor ID: 16-bit field which indicates the company
vendor as Intel.
8086h
RO
25.1.1.2 PCICMD - Command Register
Table 25-3. PCICMD - Command Register (Sheet 1 of 2)
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:29:0
Offset Start: 04h
Offset End: 05h
Size: 16 bit
Default: 0000h
Power Well: Core
Bit Range
15 : 11
10
09
08
07
06
05
04
03
Bit Acronym
Bit Description
Sticky
Reserved
INTDIS
FBE
SERREN
WCC
PER
VGAPS
PMWE
SCE
Reserved
Interrupt Disable:
0 = Enable. The function is able to generate its interrupt
to the interrupt controller.
1 = Disable. The function is not capable of generating
interrupts.
The corresponding Interrupt Status bit is not affected by
the interrupt enable.
Fast Back to Back Enable: Hardwired to‘0’.
SERR# Enable: Hardwired to‘0’.
Wait Cycle Control: Hardwired to‘0’.
Parity Error Response: Hardwired to‘0’.
VGA Palette Snoop: Hardwired to‘0’.
Postable Memory Write Enable: Hardwired to‘0’.
Special Cycle Enable: Hardwired to‘0’.
Bit Reset
Value
0h
0h
0h
0h
0h
0h
0h
0h
0h
Bit Access
RW
Intel^® EP80579 Integrated Processor Product Line Datasheet
942
August 2009
Order Number: 320066-003US