EP80579 Datasheet, PDF (934/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
24.8.2.6
Offset 16h: NDLB: Notify Data Low Byte Register
This register is in the resume well and is reset by CF9 RESET or RSMRST#.
Table 24-52. Offset 16h: NDLB: Notify Data Low Byte Register
Description:
View: PCI
Size: 8 bit
BAR: SM_BASE (IO)
Default: 00h
Bus:Device:Function: 0:31:3
Offset Start: 16h
Offset End: 16h
Power Well: Resume^a
Bit Range Bit Acronym
Bit Description
Sticky
07 : 00
This field contains the first (low) byte of data received
DATA_LOW_BYT during the Host Notify protocol of the SMBus
E
Specification. Software should only consider this field
valid when the HOST_NOTIFY_STS bit is set to 1.
a. Reset by CF9 RESET or RSMRST#.
Bit Reset
Value
00h
Bit Access
RO
24.8.2.7
Offset 17h: NDHB: Notify Data High Byte Register
This register is in the resume well and is reset by CF9 RESET or RSMRST#.
Table 24-53. Offset 17h: NDHB: Notify Data High Byte Register
Description:
View: PCI
Size: 8 bit
BAR: SM_BASE (IO)
Default: 00h
Bus:Device:Function: 0:31:3
Offset Start: 17h
Offset End: 17h
Power Well: Resume^a
Bit Range Bit Acronym
Bit Description
Sticky
07 : 00
DATA_
HIGH_BYTE
This field contains the second (high) byte of data
received during the Host Notify protocol of the SMBus
Specification. Software should only consider this field
valid when the HOST_NOTIFY_STS bit is set to 1.
a. Reset by CF9 RESET or RSMRST#.
Bit Reset
Value
00h
Bit Access
RO
Intel^® EP80579 Integrated Processor Product Line Datasheet
934
August 2009
Order Number: 320066-003US