EP80579 Datasheet, PDF (1281/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
35.9.1.12 Offset 34h: CP – Capabilities Pointer Register
The CP provides the offset to the location in configuration space where the first set of
capabilities registers is located.
Table 35-72. Offset 34h: CP: Capabilities Pointer Register
Description:
View: PCI 1
BAR: Configuration
Bus:Device:Function: M:4:0
Offset Start: 34h
Offset End: 34h
View: PCI 2
BAR: Configuration
Bus:Device:Function: M:5:0
Offset Start: 34h
Offset End: 34h
Size: 8 bit
Default: DCh
Power Well: Core
Bit Range Bit Acronym
Bit Description
07 : 00
Pointer to First Capability Structure: Value is DCh
CP
which is the config space offset of the first capability
structure.
Sticky
Bit Reset
Value
Bit Access
DCh
RO
35.9.1.13 Offset 3Ch: IRQL – Interrupt Line Register
Table 35-73. Offset 3Ch: IRQL: Interrupt Line Register
Description:
View: PCI 1
BAR: Configuration
Bus:Device:Function: M:4:0
Offset Start: 3Ch
Offset End: 3Ch
View: PCI 2
BAR: Configuration
Bus:Device:Function: M:5:0
Offset Start: 3Ch
Offset End: 3Ch
Size: 8 bit
Default: 00h
Power Well: Core
Bit Range
07 : 00
Bit Acronym
Bit Description
Sticky
IRQL
Interrupt Line: BIOS writes the interrupt routing
information to this register to indicate which input of the
interrupt controller this device is connected to.
Bit Reset
Value
0h
Bit Access
RW
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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