EP80579 Datasheet, PDF (1017/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 26-48. Offset 64h: PORTSC - Port N Status and Control Register (Sheet 2 of 5)
Description: Port 1 64 - 67h, Port 2 68 - 6Bh
View: PCI
BAR: MBAR
Bus:Device:Function: 0:29:7
Offset Start: 64h
Offset End: 67h
View: PCI
BAR: MBAR
Bus:Device:Function: 0:29:7
Offset Start: 68h
Offset End: 6Bh
Size: 32 bit
Default: 00003000h
Power Well: Suspend
Bit Range
20
19 :16
15 :14
13
12
Bit
Acronym
Bit Description
Sticky
Wake on Connect Enable:
0 = Disable. (Default).
1 = Writing this bit to a one enables the port to be sensitive
to device connects as wake-up events. When enabled to
do so, the EHC sets the PME Status bit in the Power
WKCNNT_E
Management Control/Status Register (offset 54, bit 15)
when the Current Connect Status changes from
disconnected to connected (i.e., bit 0 of this register
changes from 0 to 1).
Note: There is no support for wake from USB when in S3/S4/
S5.
PT_CTRL
Port Test Control: Default = 0000b. When this field is zero,
the port is NOT operating in a test mode. A non-zero value
indicates that it is operating in test mode and the specific test
mode is indicated by the specific value. The encoding of the
test mode bits are (0110b - 1111b are reserved):
Bits
Test Mode
0000b Test mode not enabled
0001b Test J_STATE - During this test mode the
hardware will force pre-emphasis disabled to the AFE
0010b Test K_STATE - During this test mode the
hardware will force pre-emphasis disabled to the AFE
0011b Test SE0_NAK
0100b Test Packet
0101b Test FORCE_ENABLE
Refer to USB Rev. 2.0 Specification, Chapter 7 and the EHCI
Specification, Chapter 4 for details on each test mode. The
EHC does not support the option to run the port tests while
the Run/Stop bit is a one.
Reserved Reserved.
Port Owner: Default = 1b. This bit unconditionally goes to a
0b when the Configure Flag makes a 0b to 1b transition. This
bit unconditionally goes to 1b whenever the Configure Flag
bit is zero.
System software uses this field to release ownership of the
PO
port to a selected host controller (in the event that the
attached device is not a high-speed device). Software writes
a one to this bit when the attached device is not a high-speed
device. A one in this bit means that a companion host
controller owns and controls the port. See Section 4 of the
EHCI Specification for operational details.
PP
Port Power: Hard-wired with a value of one. This indicates
that the port does have power.
Bit Reset
Value
0h
0000h
00h
1h
1h
Bit Access
RW
RW
RW
RO
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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