EP80579 Datasheet, PDF (1007/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
26.3.2.1
Offset 20h: USB2CMD - USB 2.0 Command Register
The Command Register indicates the command to be executed by the serial bus host
controller. Writing to the register causes a command to be executed.
Table 26-40. Offset 20h: USB2CMD - USB 2.0 Command Register (Sheet 1 of 2)
Description:
View: PCI
BAR: MBAR
Bus:Device:Function: 0:29:7
Offset Start: 20h
Offset End: 23h
Size: 32 bit
Default: 00080000h
Power Well: Core
Bit Range
31 :24
23 :16
15 :12
11 :08
07
06
05
Bit Acronym
Bit Description
Sticky
Reserved
ITC
Reserved
UAPM
LHCR
IAAD
ASY_SCEN
Reserved.
Interrupt Threshold Control: Default 08h. This field is
used by system software to select the maximum rate at
which the host controller will issue interrupts. The only
valid values are defined below. If software writes an
invalid value to this register, the results are undefined.
Value Maximum Interrupt Interval
00h
Reserved
01h
1 microframe
02h
2 microframes
04h
4 microframes
08h
8 microframes (default, equates to 1 ms)
10h
16 microframes (2 ms)
20h
32 microframes (4 ms)
40h
64 microframes (8 ms)
Refer to Section 4 in the EHCI Specification for interrupts
affected by this field.
Reserved.
Unimplemented Asynchronous Park Mode Bits: This
field is hardwired to 000b because the host controller does
not support this optional feature.
Light Host Controller Reset: This optional reset is not
supported and is hardwired to 0.
Interrupt on Async Advance Doorbell: This bit is used
as a doorbell by software to tell the host controller to issue
an interrupt the next time it advances asynchronous
schedule. Software must write a 1 to this bit to ring the
doorbell.
When the host controller has evicted all appropriate
cached schedule state, it sets the Interrupt on Async
Advance status bit in the USBSTS register. If the Interrupt
on Async Advance Enable bit in the USBINTR register is a
one then the host controller will assert an interrupt at the
next interrupt threshold. See the EHCI Specification for
operational details.
The host controller sets this bit to a zero after it has set
the Interrupt on Async Advance status bit in the USBSTS
register to a one.
Software must not write a one to this bit when the
asynchronous schedule is disabled. Doing so will yield
undefined results.
Asynchronous Schedule Enable: Default 0b. This bit
controls whether the host controller skips processing the
Asynchronous Schedule. Values mean:
0 = Do not process the Asynchronous Schedule
1 = Use the ASYNCLISTADDR register to access the
Asynchronous Schedule.
Bit Reset
Value
00h
08h
0h
0h
0h
0h
0h
Bit Access
RW
RO
RO
RW
RW
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
1007