EP80579 Datasheet, PDF (871/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 23-68. Offset 130h: PxSERR[0-1] – Port [0-1] Serial ATA Error Register (Sheet 2 of 2)
Description:
View: PCI
BAR: ABAR
Bus:Device:Function: 0:31:2
Offset Start: 130h, 1B0h
Offset End: 133h, 1B3h
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range
Bit Acronym
Bit Description
Sticky
Error (ERR): The ERR field contains error information for
use by host software in determining the appropriate
response to the error condition.
If one or more of bits 11:8 of this register are set, the
controller will stop the current transfer.
Bit Reset
Value
Bit Access
15 : 00
ERR
Bits Description
15:12
11
10
9
8
7:2
1
0
Reserved
Internal Error (E): The SATA controller failed due
to a master or target abort when attempting to
access system memory.
Protocol Error (P): A violation of the Serial ATA
protocol was detected.
Persistent Communication or Data Integrity
Error (C): A communication error that was not
recovered occurred that is expected to be
persistent. Persistent communications errors may
arise from faulty interconnect with the device, from
a device that has been removed or has failed, or a
number of other causes.
Transient Data Integrity Error (T): A data
integrity error occurred that was not recovered by
the interface.
Reserved
Recovered Communications Error (M):
Communications between the device and host
was temporarily lost but was re-established. This
can arise from a device temporarily being
removed, from a temporary loss of Phy
synchronization, or from other causes and may be
derived from the PhyNRdy signal between the
Phy and Link layers.
Recovered Data Integrity Error (I): A data
integrity error occurred that was recovered by the
interface through a retry operation or other
recovery action.
0000h
RWC
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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