EP80579 Datasheet, PDF (428/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 16-45. Offset 78h: DRT0 - DRAM Timing Register 0 (Sheet 5 of 7)
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:0:0
Offset Start: 78h
Offset End: 7Bh
Size: 32 bit
Default: 242AD280h
Power Well: Core
Bit Range Bit Acronym
Bit Description
DRAM RAS# to CAS# delay: This bits controls the
number of clocks inserted between a row activate
command and a read or write command to that row
Sticky
Bit Reset
Value
Bit Access
11 :09
Trcd
Encoding
000
001
010
011
Others
Number of
CMDCLK
delays
3
4
5
6
Reserved
N
001b
RW
DRAM RAS# Precharge: Time: the number of clock
cycles needed to terminate access (precharge) to an open
row of memory, and open access (activate) to the next
row.
8 :06
Trp
Encoding
000
001
010
011
Others
Number of
CMDCLK
delays
3
4
5
6
Reserved
N
010b
RW
Intel^® EP80579 Integrated Processor Product Line Datasheet
428
August 2009
Order Number: 320066-003US