EP80579 Datasheet, PDF (625/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
16.5.1.31 Offset C8h: DRAMDLLC - DDR I/O DLL Control Register
The formulas that show how the SLVLEN fields affect DQS delay timing are shown in
the DQSOFCS register definition section. The SLVLEN fields are set by hardware during
the DQS delay calibration. There are five SLVLEN fields, one for each two bytes of the
DDR I/O DQ pins. The SLVBYP bit can be toggled to reset the master DLL’s in the DDR
I/O.
Table 16-254.Offset C8h: DRAMDLLC - DDR I/O DLL Control Register
Description: DRAMDLLC: DDR I/O DLL Control
View: PCI
BAR: SMRBASE
Bus:Device:Function: 0:0:0
Offset Start: C8h
Offset End: CAh
Size: 24 bit
Default: 0DB6C0h
Power Well: Core
Bit Range
23 :22
21
20 :18
17 :15
14 :12
11 :09
8 :06
5 :00
Bit Acronym
Bit Description
Reserved
SLVBYP
SLVLEN4
SLVLEN3
SLVLEN2
SLVLEN1
SLVLEN0
Reserved
Reserved
DQS delay bypass
dqs 8 coarse DQS delay
dqs 7 & 6 coarse DQS delay
dqs 5 & 4 coarse DQS delay
dqs 3 & 2 coarse DQS delay
dqs1 & 0 coarse DQS delay
Reserved
Sticky
N
Y
Y
Y
Y
Y
Y
N
Bit Reset
Value
00b
0b
011b
011b
011b
011b
011b
000000b
Bit Access
RO
RW
RW
RW
RW
RW
RW
RO
16.5.1.32 Offset E8h: FIVESREG - Fixed 5s Pattern Register
Constant value used for debug.
Table 16-255.Offset E8h: FIVESREG - Fixed 5s Pattern Register
Description: FIVESREG: Fixed 5s Pattern
View: PCI
BAR: SMRBASE
Bus:Device:Function: 0:0:0
Offset Start: E8h
Offset End: EBh
Size: 32 bit
Default: 55555555h
Power Well: Core
Bit Range
31 :00
Bit Acronym
Bit Description
FIVES
Hardwired to 5s for read-return
Sticky
N
Bit Reset
Value
55555555h
Bit Access
RO
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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