EP80579 Datasheet, PDF (1358/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Figure 37-9. Special Descriptor Field Layout
802.1q Packets
15 thru 8
VLAN[7..0]
7 thru 5
PRI
4
CFI
3 thru 0
VLAN[11:8]
All Other Packets
15
87
0
00
00
37.5.5.4
Receive Descriptor Fetching
The descriptor fetching strategy has been designed for the EP80579’s GbE to support
larger bursts across the internal bus. This is made possible by increasing the number of
GbE hardware receive descriptors (from 8 to 64), and by modifying the fetch algorithm.
The algorithm attempts to make the best use of the internal bus by fetching a cache-
line (or more) of descriptors with each burst. The following paragraphs briefly describe
the descriptor fetch algorithm and the software control provided.
When the descriptor buffer is empty, a fetch will happen as soon as any descriptors are
made available (host writes to the tail pointer). When the descriptor buffer is nearly
empty (as defined by RXDCTL.PTHRESH) a prefetch will be performed whenever
enough valid descriptors (as defined by RXDCTL.HTHRESH) are available in host
memory and no other internal bus activity of greater priority is pending (descriptor
fetches, descriptor write-backs, or packet data transfers).
When the number of descriptors in host memory is greater than the available
descriptor buffer storage, the GbE may elect to perform a fetch which is not a multiple
of cache line size. The hardware performs this non-aligned fetch if doing so will result in
the next descriptor fetch being aligned on a cache line boundary. This allows the
descriptor fetch mechanism to be most efficient in the cases where it has fallen behind
software.
Note:
The GbE NEVER fetches descriptors beyond the descriptor TAIL pointer.
37.5.5.5
Receive Descriptor Write-Back
Processors have cache line sizes that are larger than the receive descriptor size (16
bytes). Consequently, writing back descriptor information for each received packet
would cause expensive partial cache line updates. Two mechanisms minimize the
occurrence of partial line write backs: receive descriptor packing and null descriptor
padding.
37.5.5.5.1
Receive Descriptor Packing
To maximize memory efficiency, receive descriptors are “packed” together and written
as a cache line whenever possible. Descriptors accumulate and are opportunistically
written out in cacheline-oriented chunks. Used descriptors will also be explicitly written
out under the following scenarios:
• RXDCTL.WTHRESH descriptors have been used (the specified max threshold of
unwritten used descriptors has been reached)
• The last descriptors of the allocated descriptor ring have been used (to allow the
hardware to re-align to the descriptor ring start)
• A receive timer expires (RADV or RDTR)
Intel^® EP80579 Integrated Processor Product Line Datasheet
1358
August 2009
Order Number: 320066-003US