EP80579 Datasheet, PDF (909/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 24-20. Offset 02h: HCTL: Host Control Register (Sheet 2 of 4)
Description:
View: PCI
BAR: SM_BASE (IO)
Bus:Device:Function: 0:31:3
Offset Start: 02h
Offset End: 02h
Size: 8 bit
Default: 00h
Power Well: Resume
Bit Range
05
Bit Acronym
Bit Description
Sticky
LAST_BYTE
Used for I²C Read commands as an indication that the
next byte is the last one to be received for that block.
The algorithm and usage model for this bit is as follows
(assume a message of n bytes):
1. When the software sees the BYTE_DONE_STS bit
set (bit 7 in the SMBus Host Status Register) for
each of bytes 1 through n-2 of the message, the
software should then read the Block Data Byte
Register to get the byte that was just received.
2. After reading each of bytes 1 to n-2 of the message,
the software will then clear the BYTE_DONE_STS
bit.
3. After receiving byte n-1 of the message, the
software will then set the “LAST BYTE” bit. The
software will then clear the BYTE_DONE_STS bit.
4. The CMI then receives the last byte of the message
(byte n). However, the state machine sees the LAST
BYTE bit set, and instead of sending an ACK after
receiving the last byte, it instead sends a NAK.
5. After receiving the last byte (byte n), the software
still clears the BYTE_DONE_STS bit. However, the
LAST_BYTE bit is irrelevant at that point.
Notes:
1.
This bit may be set when the TCO timer causes
the SECOND_TO_STS bit to be set. See section
Section 18.2.2.6, bit 1 for more details on that
bit. The SMBus device driver should clear the
LAST_BYTE bit (if it is set) before starting any
new command.
2.
In addition to I2C Read Commands, the
LAST_BYTE bit also causes Block Read/Write
cycles to stop prematurely (at the end of the
next byte).
Bit Reset
Value
0h
Bit Access
RW
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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