EP80579 Datasheet, PDF (1208/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 33-38. Configuration Register Summary (Sheet 2 of 2)
74h
RW
75h
RW
F0h
RW
04h
RSVD
04h
RSVD
00h
RSVD
Logical Device 6 Registers (Watchdog Timer)
30h
RW
60h
RW
61h
RW
70h
RW
00h
Enable
00h
Base I/O Address MSB
00h
Base I/O Address LSB
00h
Primary Interrupt Select
33.8.3.1
Global Control/Configuration Registers [00h - 2Fh]
The chip-level (global) registers lie in the address range [00h-2Fh]. The design MUST
use all eight bits of the ADDRESS Port for register selection. All unimplemented
registers and bits ignore writes and return zero when read.
The INDEX PORT is used to select a configuration register in the chip. The DATA PORT is
then used to access the selected register. These registers are accessible only in the
Configuration Mode.
Register
Logical Device #`
Default = 00h
Device ID
Default = 00h
Device Rev
Default = 01h
SIW Interface
Default = 01h
SIW Configuration
Default = 02h
Address
(Type)
07h
(RW)
20h
(R)
21h
(R)
28h
c
29h
(RW - bit 0,
2, 3)
(R - bit 1)
Description
Logical Device Select: A write to this register selects the current
logical device. This allows access to the control and configuration
registers for each logical device.
Device ID: A read only register which provides the Device ID.
Device Rev: A read only register which provides device revision
information.
Bit 7:1 RSVD = 0
Bit 0 LPC bus wait states
0 = Not Supported
1 = Long wait states (sync 6)
Bit 0 SIRQ enable
1 =enabled; enabled logical devices participate in interrupt
generation
0 =disabled; serial interrupts disabled
Bit 1 IRQ mode (READ ONLY, WRITES IGNORED)
1 =Continuous mode
0 =Quiet mode
Bit 3:2 UART_CLK predivide
00 = divide by 1
01 = divide by 8
10 = divide by 26
11 = reserved
Bit 7:4 RSVD = 0
Intel^® EP80579 Integrated Processor Product Line Datasheet
1208
August 2009
Order Number: 320066-003US