EP80579 Datasheet, PDF (1433/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 37-23. Bus M, Devices 2, Function 0: Summary of Gigabit Ethernet Interface
Registers Mapped Through CSRBAR Memory BAR (Sheet 2 of 4)
Offset Start Offset End
Register ID - Description
Default
Value
08F8h
0100h
2160h
2168h
2800h
2804h
2808h
2810h
2818h
2820h
2828h
282Ch
2C00h
5000h
5200h at 4h
5400h at 8h
5404h at 8h
5600h at 4h
0400h
0410h
0458h
3800h
3804h
3808h
3810h
3818h
3820h
3828h
382Ch
3830h
4000h
4004h
400Ch
4010h
4014h
4018h
401Ch
4020h
4028h
08FBh
0103h
2163h
216Bh
2803h
2807h
280Bh
2813h
281Bh
2823h
282Bh
282Fh
2C03h
5003h
5203h at 4h
5403h at 8h
5407h at 8h
5603h at 4h
0403h
0413h
045Bh
3803h
3807h
380Bh
3813h
381Bh
3823h
382Bh
382Fh
3833h
4003h
4007h
400Fh
4013h
4017h
401Bh
401Fh
4023h
402Bh
“IMC2: Error Interrupt Mask Clear Register” on page 1473
“RCTL: Receive Control Register” on page 1474
“FCRTL: Flow Control Receive Threshold Low Register” on page 1478
“FCRTH: Flow Control Receive Threshold High Register” on page 1479
“RDBAL: Receive Descriptor Base Address Low Register” on page 1480
“RDBAH: Receive Descriptor Base Address High Register” on page 1480
“RDLEN: Receive Descriptor Length Register” on page 1481
“RDH: Receive Descriptor Head Register” on page 1481
“RDT: Receive Descriptor Tail Register” on page 1482
“RDTR: RX Interrupt Delay Timer (Packet Timer) Register” on page 1483
“RXDCTL: Receive Descriptor Control Register” on page 1483
“RADV: Receive Interrupt Absolute Delay Timer Register” on page 1485
“RSRPD: Receive Small Packet Detect Interrupt Register” on page 1486
“RXCSUM: Receive Checksum Control Register” on page 1487
“MTA[0-127] – 128 Multicast Table Array Registers” on page 1488
“RAL[0-15] - Receive Address Low Register” on page 1488
“RAH[0-15] - Receive Address High Register” on page 1489
“VFTA[0-127] - 128 VLAN Filter Table Array Registers” on page 1490
“TCTL: Transmit Control Register” on page 1491
“TIPG: Transmit IPG Register” on page 1493
“AIT: Adaptive IFS Throttle Register” on page 1495
“TDBAL: Transmit Descriptor Base Address Low Register” on page 1496
“TDBAH: Transmit Descriptor Base Address High Register” on page 1496
“TDLEN: Transmit Descriptor Length Register” on page 1497
“TDH: Transmit Descriptor Head Register” on page 1497
“TDT: Transmit Descriptor Tail Register” on page 1498
“TIDV: Transmit Interrupt Delay Value Register” on page 1499
“TXDCTL: Transmit Descriptor Control Register” on page 1500
“TADV: Transmit Absolute Interrupt Delay Value Register” on page 1502
“TSPMT: TCP Segmentation Pad And Minimum Threshold Register” on page 1504
“CRCERRS: CRC Error Count Register” on page 1505
“ALGNERRC: Alignment Error Count Register” on page 1506
“RXERRC: Receive Error Count Register” on page 1506
“MPC: Missed Packet Count Register” on page 1507
“SCC: Single Collision Count Register” on page 1507
“ECOL: Excessive Collisions Count Register” on page 1508
“MCC: Multiple Collision Count Register” on page 1508
“LATECOL: Late Collisions Count Register” on page 1509
“COLC: Collision Count Register” on page 1509
00000000h
00000000h
00000000h
00000000h
XXXXXXX0h
XXXXXXXXh
00000000h
00000000h
00000000h
00000000h
00010000h
00000000h
00000000h
00000000h
XXXX_XXXXh
XXXXXXXXh
000XXXXXh
XXXXXXXXh
00000008h
00602008h
00000000h
XXXXXXX0h
XXXXXXXXh
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
01000400h
00000000h
00000000h
00000000h
00000000h
0000h
00000000h
00000000h
00000000h
00000000h
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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